公开(公告)号：US20240203797A1

公开(公告)日：2024-06-20

申请号：US18081207

申请日：2022-12-14

Applicant: Tokyo Electron Limited

Inventor： Andrew WELOTH ,  Daniel FULFORD ,  Anthony SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton DEVILLIERS ,  David CONKLIN

IPC: H01L21/66 ,  G03F7/00 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L22/20 ,  G03F7/0035 ,  H01L21/02002 ,  H01L21/67092 ,  H01L21/67288

Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

公开(公告)号：US20240203778A1

公开(公告)日：2024-06-20

申请号：US18085354

申请日：2022-12-20

Applicant: Tokyo Electron Limited

Inventor： David POWER ,  David CONKLIN ,  Anthony SCHEPIS ,  Andrew WELOTH ,  Anton DEVILLIERS

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/681 ,  H01L21/67265 ,  H01L21/6835 ,  H01L23/544 ,  H01L2221/68363 ,  H01L2223/54426

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

公开(公告)号：US20230367217A1

公开(公告)日：2023-11-16

申请号：US18354388

申请日：2023-07-18

Applicant: Tokyo Electron Limited

Inventor： Jodi GRZESKOWIAK ,  Anthony SCHEPIS ,  Anton DEVILLIERS

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  G03F7/004 ,  G03F7/11

CPC classification number: G03F7/094 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/3085 ,  G03F7/0045 ,  H01L21/3088 ,  G03F7/11 ,  G03F7/091 ,  H01L21/3086

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

公开(公告)号：US20200328103A1

公开(公告)日：2020-10-15

申请号：US16528099

申请日：2019-07-31

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Anthony SCHEPIS ,  Anton J. deVILLIERS

IPC: H01L21/67 ,  H01L23/544 ,  H01L23/528 ,  H01L21/027

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

公开(公告)号：US20200328102A1

公开(公告)日：2020-10-15

申请号：US16528043

申请日：2019-07-31

Applicant: Tokyo Electron Limited

Inventor： Anthony SCHEPIS ,  Anton J. deVILLIERS ,  H. Jim FULFORD

IPC: H01L21/67 ,  H01L23/544 ,  H01L21/027

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique identifier.

公开(公告)号：US20210351053A1

公开(公告)日：2021-11-11

申请号：US17381297

申请日：2021-07-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Anthony SCHEPIS ,  Anton J. DEVILLIERS

IPC: H01L21/67 ,  H01L23/544 ,  H01L21/027 ,  H01L23/528

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

公开(公告)号：US20210088907A1

公开(公告)日：2021-03-25

申请号：US17032980

申请日：2020-09-25

Applicant: Tokyo Electron Limited

Inventor： Jodi GRZESKOWIAK ,  Anthony SCHEPIS ,  Anton DEVILLIERS

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  G03F7/11 ,  G03F7/004

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.