公开(公告)号：US12255063B2

公开(公告)日：2025-03-18

申请号：US17259244

申请日：2019-07-18

Applicant: Tokyo Electron Limited

Inventor： Hayato Tanoue ,  Takashi Uno ,  Satoshi Ookawa ,  Suguru Enokida

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687

Abstract: A substrate processing system configured to process a substrate includes a first modifying apparatus configured to form, in a combined substrate in which a front surface of a first substrate and a front surface of a second substrate are bonded to each other, an internal modification layer elongated within the first substrate in a plane direction from a center of the first substrate toward at least an edge portion of the first substrate as a removing target; a second modifying apparatus configured to form, within the first substrate, an edge modification layer elongated in a thickness direction of the first substrate along a boundary between the edge portion and a central portion of the first substrate; and a separating apparatus configured to separate a portion of the first substrate at a rear surface side, starting from the internal modification layer.

公开(公告)号：US09984905B2

公开(公告)日：2018-05-29

申请号：US15252422

申请日：2016-08-31

Applicant: Tokyo Electron Limited

Inventor： Masahiro Nakaharada ,  Yoji Sakata ,  Akira Miyata ,  Shinichi Hayashi ,  Suguru Enokida ,  Tsunenaga Nakashima

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/687 ,  H01L21/02 ,  H01L21/66 ,  G03F7/20

CPC classification number: H01L21/67051 ,  G03F7/70691 ,  H01L21/02043 ,  H01L21/67046 ,  H01L21/67173 ,  H01L21/67178 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/67225 ,  H01L21/67242 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67706 ,  H01L21/67748 ,  H01L21/6875 ,  H01L22/20

Abstract: An interface station of a coating and developing treatment system has: a cleaning unit cleaning at least a rear surface of a wafer before the wafer is transferred into an exposure apparatus; an inspection unit inspecting the rear surface of the cleaned wafer whether the wafer is exposable, before it is transferred into the exposure apparatus; wafer transfer mechanisms including arms transferring the wafer between the units and a wafer transfer control part controlling operations of the wafer transfer mechanisms. When it is determined that a state of the wafer becomes an exposable state by re-cleaning in the cleaning unit as a result of the inspection, the wafer transfer control part controls the wafer transfer mechanisms to transfer the wafer again to the cleaning unit.

公开(公告)号：US09984904B2

公开(公告)日：2018-05-29

申请号：US15252374

申请日：2016-08-31

Applicant: Tokyo Electron Limited

Inventor： Masahiro Nakaharada ,  Yoji Sakata ,  Akira Miyata ,  Shinichi Hayashi ,  Suguru Enokida ,  Tsunenaga Nakashima

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/687 ,  H01L21/02 ,  H01L21/66 ,  G03F7/20

CPC classification number: H01L21/67051 ,  G03F7/70691 ,  H01L21/02043 ,  H01L21/67046 ,  H01L21/67173 ,  H01L21/67178 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/67225 ,  H01L21/67242 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67706 ,  H01L21/67748 ,  H01L21/6875 ,  H01L22/20

Abstract: An interface station of a coating and developing treatment system has: a cleaning unit cleaning at least a rear surface of a wafer before the wafer is transferred into an exposure apparatus; an inspection unit inspecting the rear surface of the cleaned wafer whether the wafer is exposable, before it is transferred into the exposure apparatus; wafer transfer mechanisms including arms transferring the wafer between the units and a wafer transfer control part controlling operations of the wafer transfer mechanisms. When it is determined that a state of the wafer becomes an exposable state by re-cleaning in the cleaning unit as a result of the inspection, the wafer transfer control part controls the wafer transfer mechanisms to transfer the wafer again to the cleaning unit.

公开(公告)号：US09460942B2

公开(公告)日：2016-10-04

申请号：US13663846

申请日：2012-10-30

Applicant: Tokyo Electron Limited

Inventor： Masahiro Nakaharada ,  Yoji Sakata ,  Akira Miyata ,  Shinichi Hayashi ,  Suguru Enokida ,  Tsunenaga Nakashima

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/687

CPC classification number: H01L21/67051 ,  G03F7/70691 ,  H01L21/02043 ,  H01L21/67046 ,  H01L21/67173 ,  H01L21/67178 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/67225 ,  H01L21/67242 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67706 ,  H01L21/67748 ,  H01L21/6875 ,  H01L22/20

Abstract: An interface station of a coating and developing treatment system has: a cleaning unit cleaning at least a rear surface of a wafer before the wafer is transferred into an exposure apparatus; an inspection unit inspecting the rear surface of the cleaned wafer whether the wafer is exposable, before it is transferred into the exposure apparatus; wafer transfer mechanisms including arms transferring the wafer between the units and a wafer transfer control part controlling operations of the wafer transfer mechanisms. When it is determined that a state of the wafer becomes an exposable state by re-cleaning in the cleaning unit as a result of the inspection, the wafer transfer control part controls the wafer transfer mechanisms to transfer the wafer again to the cleaning unit.

Abstract translation: 涂装和显影处理系统的界面站具有：在将晶片转移到曝光装置之前，清洁单元至少清洁晶片的后表面; 检查单元，在将其转印到曝光装置之前，检查清洁晶片的背面是否可曝光; 晶片传送机构包括在晶片传送机构之间转移晶片的晶片传送控制部件。 当通过检查结果确定晶片的状态通过重新清洁在清洁单元中时，晶片转移控制部分控制晶片传送机构将晶片再次传送到清洁单元。

公开(公告)号：US09417529B2

公开(公告)日：2016-08-16

申请号：US14626295

申请日：2015-02-19

Applicant: TOKYO ELECTRON LIMITED

Inventor： Nobuaki Matsuoka ,  Akira Miyata ,  Shinichi Hayashi ,  Suguru Enokida ,  Hiroshi Tomita ,  Makoto Hayakawa ,  Tatsuhei Yoshida

IPC: G03B27/52 ,  G03F7/16 ,  H01L21/67

CPC classification number: G03F7/16 ,  H01L21/6715

Abstract: In one embodiment, a coating and developing apparatus includes a processing block having two early-stage coating unit blocks, two later-stage coating unit blocks and two developing unit blocks, each unit blocks being vertically stacked on each other, The apparatus has at least two operation modes M1 and M2 adapted for abnormality. In mode M1 the processing module that processed the abnormal substrate in the developing unit blocks is identified, and subsequent substrates are transported to the processing module or modules, of the same type as the identified processing module, other than the identified processing module. In mode M2, the developing unit block that processed the abnormal substrate is identified, and subsequent substrates are transported to the developing unit block other than the identified developing unit block.

Abstract translation: 在一个实施例中，涂层和显影装置包括具有两个早期涂层单元块，两个后期涂层单元块和两个显影单元块的处理块，每个单元块彼此垂直堆叠。该装置至少具有 适用于异常的两种操作模式M1和M2。 在模式M1中，识别处理显影单元块中的异常衬底的处理模块，并且随后的衬底被传送到除了所识别的处理模块之外的与所识别的处理模块相同类型的处理模块。 在模式M2中，识别处理异常衬底的显影单元块，并且随后的衬底被传送到除了所识别的显影单元块之外的显影单元块。

公开(公告)号：US09082800B2

公开(公告)日：2015-07-14

申请号：US13623189

申请日：2012-09-20

Applicant: Tokyo Electron Limited

Inventor： Suguru Enokida ,  Masahiro Nakaharada ,  Hidekazu Kiyama ,  Naruaki Iida ,  Akira Miyata

IPC: H01L21/677 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/67766 ,  H01L21/67155 ,  H01L21/67178 ,  H01L21/67769 ,  H01L21/68707

Abstract: A substrate treatment system comprise a treatment station having a plurality of treatment units provided at multiple tiers in an up-down direction, a cassette mounting table on which a cassette housing a plurality of wafers W is mounted, and a wafer transfer mechanism arranged between the treatment station and the cassette mounting table, wherein a delivery block in which a plurality of delivery units are provided at multiple tiers is provided between the treatment station and the wafer transfer mechanism, the delivery units temporarily housing a wafer to be transferred between the cassette mounting table and the treatment station and a wafer to be transferred between the tiers of the treatment units. The wafer transfer mechanism includes a first transfer arm that transfers a wafer between the cassette mounting table and the delivery block, and a second transfer arm that transfers a wafer between the tiers of the delivery units.

Abstract translation: 基板处理系统包括处理台，该处理台具有设置在上下方向的多层的多个处理单元，安装有多个晶片W的盒子的盒安装台，以及布置在 处理台和盒安装台，其中在处理站和晶片传送机构之间设置有多个传送单元设置在多层的传送块，传送单元暂时容纳要在盒安装件 桌子和治疗台以及待处理单元层之间转移的晶片。 晶片传送机构包括在盒安装台和传送块之间传送晶片的第一传送臂和在传送单元的各层之间传送晶片的第二传送臂。