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公开(公告)号：US07057912B2
公开(公告)日：2006-06-06
申请号：US10755333
申请日：2004-01-13
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using the same current path as that for a search operation, thereby providing a highly integrated array without reducing the original search speed. A rewrite data line is provided in parallel with a match line, and rewrite transistors are inserted between the rewrite data line and the storage nodes within each dynamic CAM cell. With this cell configuration, the data stored at each storage node is read out to the match line one at a time and rewritten through the rewrite data line to carry out a refresh operation.
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公开(公告)号：US08319204B2
公开(公告)日：2012-11-27
申请号：US12373185
申请日：2006-07-21
申请人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
发明人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.
摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。
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公开(公告)号：US20090039335A1
公开(公告)日：2009-02-12
申请号：US12162769
申请日：2006-02-09
IPC分类号： H01L45/00
CPC分类号： H01L27/101 , G11C13/0004 , G11C13/0011 , G11C2213/79 , H01L27/0688 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： On an insulating film (31) in which a plug (35) is embedded, a second component releasing region (45) made of a first component and a second component, a solid electrolyte region (46) made of chalcogenide and an upper electrode region (47) are sequentially formed. The second component releasing region (45) made of a first component and a second component is composed of dome-shaped electrode portions (43) and an insulating film (44) burying the peripheries of the electrode portions (43), and at least one electrode portion (43) exists on the plug (34). The electrode portion (43) is composed of a first portion made of the first component such as tantalum oxide that is stable even when electric field is applied thereto and a second portion made of the second component such as copper or silver that is easily diffused in the solid electrolyte region (42) and moves therein by the application of an electric field. The second component supplied from the electrode portion (43) moves in the solid electrolyte region (46), thereby storing the information.
摘要翻译： 在其中嵌入有插塞（35）的绝缘膜（31）上，由第一部件和第二部件制成的第二部件释放区域（45），由硫族化物制成的固体电解质区域（46）和上部电极区域 （47）。 由第一部件和第二部件制成的第二部件释放区域（45）由埋入电极部分（43）的周边的圆顶状电极部分（43）和绝缘膜（44）组成，并且至少一个 电极部分（43）存在于插头（34）上。 电极部（43）由第一部分（例如氧化钽）构成的第一部分，即使施加电场也是稳定的，而由诸如铜或银的第二部分制成的第二部分容易扩散 固体电解质区域（42）并通过施加电场而在其中移动。 从电极部（43）供给的第二部件在固体电解质区域（46）中移动，从而存储信息。
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公开(公告)号：US20060198210A1
公开(公告)日：2006-09-07
申请号：US11401261
申请日：2006-04-11
IPC分类号： G11C7/06
CPC分类号： G11C15/04 , G11C15/043
摘要： A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using the same current path as that for a search operation, thereby providing a highly integrated array without reducing the original search speed. A rewrite data line is provided in parallel with a match line, and rewrite transistors are inserted between the rewrite data line and the storage nodes within each dynamic CAM cell. With this cell configuration, the data stored at each storage node is read out to the match line one at a time and rewritten through the rewrite data line to carry out a refresh operation.
摘要翻译： 提供由三元动态CAM单元组成的T-CAM阵列，每个三角形动态CAM单元包括多个晶体管。 在使用与搜索操作相同的当前路径的同时读取存储的数据到匹配行时，可以执行刷新操作，从而提供高度集成的阵列而不降低原始搜索速度。 与匹配线并行提供重写数据线，并且在每个动态CAM单元内的重写数据线和存储节点之间插入重写晶体管。 利用该单元配置，将存储在每个存储节点处的数据一次读出到匹配行，并通过重写数据行重写以执行刷新操作。
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25.发明授权公开(公告)号：US07366001B2
公开(公告)日：2008-04-29
申请号：US11019321
申请日：2004-12-23
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。
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公开(公告)号：US07881088B2
公开(公告)日：2011-02-01
申请号：US12367108
申请日：2009-02-06
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。
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公开(公告)号：US20050157526A1
公开(公告)日：2005-07-21
申请号：US11019321
申请日：2004-12-23
IPC分类号： G11C11/401 , G11C11/56 , G11C15/04 , G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。
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公开(公告)号：US07894232B2
公开(公告)日：2011-02-22
申请号：US12427392
申请日：2009-04-21
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。
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公开(公告)号：US08130575B2
公开(公告)日：2012-03-06
申请号：US13207611
申请日：2011-08-11
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。
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公开(公告)号：US08482997B2
公开(公告)日：2013-07-09
申请号：US13366329
申请日：2012-02-05
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。
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