公开(公告)号：US20120110414A1

公开(公告)日：2012-05-03

申请号：US13287488

申请日：2011-11-02

申请人： Torsten Hinz ,  Gerhard Risse

发明人： Torsten Hinz ,  Gerhard Risse

IPC分类号： G06F11/10 ,  G06F12/00

CPC分类号： G06F11/1044 ,  G06F11/1666 ,  G06F11/20 ,  G11C5/04 ,  G11C2029/0409

摘要： A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

摘要翻译： 存储器装置包括第一存储器模块和第二存储器模块。 要写入存储器装置的信息项目被写入第一存储器模块和第二存储器模块。 当读取时，借助于与第一地址不同的第二地址，通过第一地址或第二存储器模块从第一存储器模块读取信息项。 随后检查信息项是否有缺陷。 如果是这种情况，则从相应的其他存储器模块读取信息项。

公开(公告)号：US20100030944A1

公开(公告)日：2010-02-04

申请号：US12182826

申请日：2008-07-30

申请人： Torsten Hinz

发明人： Torsten Hinz

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G11C7/22 ,  G06F12/0864 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7208 ,  G11C16/32 ,  G11C2207/2236 ,  G11C2207/2245

摘要： A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory.

摘要翻译： 公开了一种用于将数据存储在闪存驱动器中的方法和存储装置。 为了增加数据吞吐量，驱动器包括高速缓冲存储器，其包括标签存储器和经由多个通道耦合到高速缓冲存储器的多个闪存器件。

公开(公告)号：US20090037764A1

公开(公告)日：2009-02-05

申请号：US11740762

申请日：2007-04-26

申请人： Torsten Hinz ,  Gerhard Risse

发明人： Torsten Hinz ,  Gerhard Risse

IPC分类号： G06F11/00 ,  G06F12/06

CPC分类号： G06F11/1044 ,  G06F11/1666 ,  G06F11/20 ,  G11C5/04 ,  G11C2029/0409

摘要： A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

摘要翻译： 存储器装置包括第一存储器模块和第二存储器模块。 要写入存储器装置的信息项目被写入第一存储器模块和第二存储器模块。 当读取时，借助于与第一地址不同的第二地址，通过第一地址或第二存储器模块从第一存储器模块读取信息项。 随后检查信息项是否有缺陷。 如果是这种情况，则从相应的其他存储器模块读取信息项。

公开(公告)号：US07456665B2

公开(公告)日：2008-11-25

申请号：US11464999

申请日：2006-08-16

申请人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

发明人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03L7/0805 ,  H03L7/0814

摘要： A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

摘要翻译： 公开了一种用于从输入信号产生相移的，特别是相位延迟的输出信号的移相器。 在一个实施例中，移相器包括第一延迟线和至少一个另外的延迟线，其具有分别级联的延迟元件，其形成U形信号路径，至少一个延迟元件沿着该延伸元件被控制为可选地打开或关闭 。 位于其输入侧的相位鉴别器可以施加来自延迟线之一的时钟信号和信号，其输出侧与延迟元件的相应控制输入相连。 时钟信号也可以被施加到第一延迟线，使得由相位鉴别器和至少一个延迟线形成反馈回路。 输入信号可以施加到信号输出不与鉴相器连接的延迟线，并且可以从其输出输出信号。

公开(公告)号：US06876710B1

公开(公告)日：2005-04-05

申请号：US09619973

申请日：2000-07-20

申请人： Armin Pitzer ,  Torsten Hinz

发明人： Armin Pitzer ,  Torsten Hinz

IPC分类号： H03L7/081 ,  H03L7/093 ,  H03L7/099 ,  H04J3/06 ,  H04L25/00

CPC分类号： H03L7/0991 ,  H03L7/0814 ,  H03L7/093 ,  H04J3/0626

摘要： A digitally controlled circuit for reducing the phase modulation of a signal. The circuit has a multiphase clock generator that produces n phases of a clock that is m-times the signal. The circuit further has a multiplexer with n inputs for the n phases of the clock and with one output which supplies the output signal. The output signal and the signal are connected to the inputs of a phase comparator. The output signal of the comparator is supplied to a sigma-delta modulator whose output signals are used for controlling the multiplexer. A jittered input signal is compared in the phase comparator with a master clock. The determined phase difference is integrated in a sigma-delta modulator. The aim of the circuit is to generate a clock without jitter, digitally and without using external components. This circuit provides 20 dB/decade attenuation of the jitter received in the SYNC signal, based on the P-regulator characteristic.

摘要翻译： 一种用于减少信号相位调制的数字控制电路。 该电路具有多相时钟发生器，其产生与信号m倍的时钟的n相。 该电路还具有一个多路复用器，其具有用于时钟的n个相位的n个输入端，并且一个输出端提供输出信号。 输出信号和信号连接到相位比较器的输入。 比较器的输出信号被提供给一个Σ-Δ调制器，其输出信号用于控制多路复用器。 在相位比较器中将抖动的输入信号与主时钟进行比较。 确定的相位差集成在Σ-Δ调制器中。 该电路的目的是生成无抖动的时钟，数字化并且不使用外部组件。 该电路基于P调节器特性，提供在SYNC信号中接收的抖动的20 dB /十倍衰减。

公开(公告)号：US20050063494A1

公开(公告)日：2005-03-24

申请号：US10492390

申请日：2002-09-04

申请人： Peter Gregorius ,  Torsten Hinz

发明人： Peter Gregorius ,  Torsten Hinz

IPC分类号： H04L7/00 ,  H04L7/033 ,  H03D1/00

CPC分类号： H04L7/033 ,  H04L7/0083

摘要： In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal (RX), having a clock-signal recovery unit (3) for recovering a clock signal belonging to the transmitted data from the received data signal, and having a data reconstruction unit (2) for reconstructing the transmitted data from the received data signal using the recovered clock signal (fCLK), and for emitting a data stream (DATA) which is synchronised with the recovered clock signal. A detector unit (9) detects an error state in the received data signal (RX) which prevents the data from being reconstructed reliably, switching means having a digital phase-locked lock (13) being provided to enable a signal having a clock rate which corresponds to the mean value of the clock signal (fCLK) previously recovered by the clock-signal recovery unit (3) to be fed, as a reference signal, to a phase-locked loop of the clock-signal recovery unit (3) in this event in place of the received data signal, thus ensuring that the phase-locked loop of the clock-signal recovery unit (3) will continue to oscillate properly even in this event.

摘要翻译： 在特别用于发送光数据的收发器中，提供了一种用于从接收的数据信号（RX）重建数据的装置，具有用于恢复属于发送数据的时钟信号的时钟信号恢复单元（3） 并且具有用于使用恢复的时钟信号（fCLK）从接收到的数据信号重建发送的数据的数据重建单元（2），并且用于发出与恢复的时钟同步的数据流（DATA） 信号。 检测器单元（9）检测接收到的数据信号（RX）中的错误状态，其阻止数据被可靠地重建，具有数字锁相锁（13）的开关装置被提供以使得具有时钟速率的信号 对应于由时钟信号恢复单元（3）预先恢复的时钟信号（fCLK）的平均值作为参考信号被馈送到时钟信号恢复单元（3）的锁相环 该事件代替接收到的数据信号，从而确保即使在这种情况下时钟信号恢复单元（3）的锁相环仍将适当地振荡。