公开(公告)号：US07339407B2

公开(公告)日：2008-03-04

申请号：US11360988

申请日：2006-02-23

申请人： Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

发明人： Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0814 ,  H03L7/087

摘要： The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

摘要翻译： 本发明涉及一种用于提供周期性输入信号的可调时间延迟的DLL电路，所述电路具有可串联连接并形成延迟链的可控延迟元件，具有相位检测器，以便在此基础上产生控制信号 和延迟链延迟的周期信号，基于控制信号调整每个延迟元件的延迟，并且具有选择单元，其分别连接到延迟链中的一个延迟 元件，以便根据所提供的选择变量将来自延迟元件之一的输出信号施加到DLL电路的输出;以及补偿电路，其修改选择信号，使得附加延迟（即 至少由选择单元引起的）周期性输入信号与来自DLL电路的输出信号进行补偿。

公开(公告)号：US20060197567A1

公开(公告)日：2006-09-07

申请号：US11360988

申请日：2006-02-23

申请人： Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

发明人： Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0814 ,  H03L7/087

摘要： The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

摘要翻译： 本发明涉及一种用于提供周期性输入信号的可调时间延迟的DLL电路，所述电路具有可串联连接并形成延迟链的可控延迟元件，具有相位检测器，以便在此基础上产生控制信号 和延迟链延迟的周期信号，基于控制信号调整每个延迟元件的延迟，并且具有选择单元，其分别连接到延迟链中的一个延迟 元件，以便根据所提供的选择变量将来自延迟元件之一的输出信号施加到DLL电路的输出;以及补偿电路，其修改选择信号，使得附加延迟（即 至少由选择单元引起的）周期性输入信号与来自DLL电路的输出信号进行补偿。

公开(公告)号：US07456665B2

公开(公告)日：2008-11-25

申请号：US11464999

申请日：2006-08-16

申请人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

发明人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03L7/0805 ,  H03L7/0814

摘要： A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

摘要翻译： 公开了一种用于从输入信号产生相移的，特别是相位延迟的输出信号的移相器。 在一个实施例中，移相器包括第一延迟线和至少一个另外的延迟线，其具有分别级联的延迟元件，其形成U形信号路径，至少一个延迟元件沿着该延伸元件被控制为可选地打开或关闭 。 位于其输入侧的相位鉴别器可以施加来自延迟线之一的时钟信号和信号，其输出侧与延迟元件的相应控制输入相连。 时钟信号也可以被施加到第一延迟线，使得由相位鉴别器和至少一个延迟线形成反馈回路。 输入信号可以施加到信号输出不与鉴相器连接的延迟线，并且可以从其输出输出信号。

公开(公告)号：US20070115035A1

公开(公告)日：2007-05-24

申请号：US11464999

申请日：2006-08-16

申请人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

发明人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03L7/0805 ,  H03L7/0814

摘要： A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

摘要翻译： 公开了一种用于从输入信号产生相移的，特别是相位延迟的输出信号的移相器。 在一个实施例中，移相器包括第一延迟线和至少一个另外的延迟线，其具有分别级联的延迟元件，其形成U形信号路径，沿着该延伸元件至少一个延迟元件被控制为可选地打开或关闭 。 位于其输入侧的相位鉴别器可以施加来自延迟线之一的时钟信号和信号，其输出侧与延迟元件的相应控制输入相连。 时钟信号也可以被施加到第一延迟线，使得由相位鉴别器和至少一个延迟线形成反馈回路。 输入信号可以施加到信号输出不与鉴相器连接的延迟线，并且可以从其输出输出信号。

公开(公告)号：US20120140930A1

公开(公告)日：2012-06-07

申请号：US13248346

申请日：2011-09-29

申请人： Christoph Braun ,  Thomas Duda ,  Torsten Hinz

发明人： Christoph Braun ,  Thomas Duda ,  Torsten Hinz

IPC分类号： H04R5/00

CPC分类号： H04S5/00 ,  H04S2400/07

摘要： A circuit for operating loudspeakers includes a first, second, third and fourth loudspeaker circuit, having one input each for injecting a signal and one output each for connecting a loudspeaker input. The loudspeaker circuits are designed to amplify the injected signal and to provide the amplified signal at the outputs thereof. The loudspeaker circuits can, for example, be used for a 2.1 sound system. The three channels for a 2.1 sound system can be implemented by an amplifier circuit with four loudspeaker circuits, one loudspeaker circuit each being required for the two stereo channels left and right. A subwoofer channel can be driven differentially by two loudspeaker circuits. The stereo channels are, by contrast, only still connected to one loudspeaker circuit each, and so the stereo channels require at least one further common ground cable.

摘要翻译： 用于操作扬声器的电路包括第一，第二，第三和第四扬声器电路，每个扬声器电路具有一个输入，每个用于注入信号，每个输入用于连接扬声器输入。 扬声器电路被设计成放大注入的信号并在其输出处提供放大的信号。 扬声器电路可以例如用于2.1声音系统。 一个2.1音响系统的三个通道可以通过一个具有四个扬声器电路的放大器电路实现，一个扬声器电路需要两个立体声通道左右。 低音炮通道可以通过两个扬声器电路进行差分驱动。 相比之下，立体声通道每个仍然连接到一个扬声器电路，因此立体声通道需要至少一个另外的公共接地电缆。

公开(公告)号：US08046530B2

公开(公告)日：2011-10-25

申请号：US12244587

申请日：2008-10-02

申请人： Torsten Hinz

发明人： Torsten Hinz

IPC分类号： G06F13/00

CPC分类号： G06F12/0246 ,  G06F2212/7209 ,  G11C16/102

摘要： An embodiment of the invention relates to a nonvolatile mass storage device such as a flash memory device formed with erase blocks partitioned into memory management blocks. An erase block is identified containing at least a minimum number of management blocks marked invalid, from which data is copied, merged, and stored in a new management block. The erase block is then erased. Erase blocks containing at least the minimum number of invalid management blocks may be erased until a minimum amount of management blocks is free. Alternatively, all erase blocks containing at least the minimum number of invalid management blocks may be erased. A management table listing the number of invalid management blocks in erase blocks may be included in the mass storage device. Preferably, the new management block for storage of the merged data is located in an erase block different from the identified erase block.

摘要翻译： 本发明的一个实施例涉及一种非易失性大容量存储装置，例如闪存装置，其形成有划分成存储器管理块的擦除块。 识别出包含标记为无效的至少最少数量的管理块的擦除块，从该数据复制，合并和存储在新的管理块中。 然后擦除擦除块。 至少包含最少数量的无效管理块的擦除块可能被擦除，直到最少量的管理块是空闲的。 或者，可以擦除包含至少最小数量的无效管理块的所有擦除块。 在大容量存储装置中可以包括列出擦除块中的无效管理块的数量的管理表。 优选地，用于存储合并数据的新管理块位于与所识别的擦除块不同的擦除块中。

公开(公告)号：US20100030999A1

公开(公告)日：2010-02-04

申请号：US12184837

申请日：2008-08-01

申请人： Torsten Hinz

发明人： Torsten Hinz

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7201

摘要： An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with pointers to locations of the memory management blocks. A volatile memory device is included with an address index table formed with pointers to the pointers to the locations of the memory management blocks. The address index table is stored in the nonvolatile memory upon loss of bias voltage. Changes to the address translation table are accumulated in the volatile memory and written to the address translation table when at least a minimum quantity of the changes has been accumulated. The changes to the logical block address translation table accumulated in the volatile memory are written to a page in the address translation table after prior data in the page has been updated, written to another page, and then erased.

摘要翻译： 本发明的实施例涉及包括具有多个存储器管理块的非易失性存储器件和形成有指向存储器管理块的位置的地址转换表的大容量存储器件。 易失性存储器件包括地址索引表，该地址索引表由指向存储器管理块的位置的指针形成。 当偏置电压丢失时，地址索引表存储在非易失性存储器中。 当至少已经累积了最小量的变化时，地址转换表的变化被累积在易失性存储器中并写入地址转换表。 累积在易失性存储器中的逻辑块地址转换表的改变在页面中的先前数据被更新，被写入另一个页面之后被写入地址转换表中的页面，然后被擦除。

公开(公告)号：US20090040082A1

公开(公告)日：2009-02-12

申请号：US12179286

申请日：2008-07-24

申请人： Torsten Hinz ,  Otto Schumacher ,  Patrick Runkel ,  Russell Homer

发明人： Torsten Hinz ,  Otto Schumacher ,  Patrick Runkel ,  Russell Homer

IPC分类号： H03M9/00

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107 ,  H03M9/00

摘要： A device for processing binary data comprises at least one transmission link having an input for receiving a serial bit stream and an output for forwarding bits in a parallel format, and a serial/parallel converter providing n≧2 successive data bits of the serial bit stream as n-bit data words in the parallel format. The serial/parallel converter comprises a 1-to-n demultiplexer which is constructed and controllable in such a manner that the successive data bits of the serial bit stream appear in succession at intervals equal to a bit period TB cyclically at n data outputs and remain latched at the respective data output until a data bit appears again at the relevant data output and a relatching circuit with latching elements which receive the signals from the data outputs of the demultiplexer at which the first k data bits of each cycle appear and which are enabled in each case at a time which is between the beginning of the latching of the last data bit and the end of the latching of the first data bit of the relevant cycle in the demultiplexer, wherein 1≦k

摘要翻译： 一种用于处理二进制数据的装置包括至少一个具有用于接收串行比特流的输入和用于以并行格式转发比特的输出的传输链路，以及串行/并行转换器，其提供串行比特的n≥2个连续数据比特 流作为并行格式的n位数据字。 串行/并行转换器包括1对n解复用器，其被构造和可控制，使得串行比特流的连续数据位以n个数据输出周期性地等于比特周期TB的间隔连续出现并保持 锁存在相应的数据输出，直到数据位再次出现在相关数据输出端，并且具有锁存元件的重合电路，该锁存元件接收来自每个周期的第一个k个数据位的多路复用器的数据输出端的信号， 在每种情况下，在解锁器中最后数据位的锁存开始和相关周期的第一数据位的锁存结束之间的时间，其中1 <= k

公开(公告)号：US08904083B2

公开(公告)日：2014-12-02

申请号：US12182826

申请日：2008-07-30

申请人： Torsten Hinz

发明人： Torsten Hinz

IPC分类号： G06F12/00 ,  G11C7/22 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G11C16/32

CPC分类号： G11C7/22 ,  G06F12/0864 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7208 ,  G11C16/32 ,  G11C2207/2236 ,  G11C2207/2245

摘要： A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory.

摘要翻译： 公开了一种用于将数据存储在闪存驱动器中的方法和存储装置。 为了增加数据吞吐量，驱动器包括高速缓冲存储器，其包括标签存储器和经由多个通道耦合到高速缓冲存储器的多个闪存器件。

公开(公告)号：US20120242522A1

公开(公告)日：2012-09-27

申请号：US13070293

申请日：2011-03-23

申请人： Torsten Hinz

发明人： Torsten Hinz

IPC分类号： H03M3/00 ,  H03M1/66 ,  H03M1/00

CPC分类号： H03M1/822 ,  H03F3/217 ,  H03H17/0283 ,  H03H17/04

摘要： In an embodiment, an oversampled data converter includes a lowpass filter having a filter stage comprising a dynamic limiter, where the dynamic limiter having a limit set by an signal level at an input to the oversampled data converter. The oversampled data converter also includes a quantizing block comprising an input coupled to an output of the lowpass filter and an output coupled to an input of the lowpass filter.

摘要翻译： 在一个实施例中，过采样数据转换器包括具有滤波器级的低通滤波器，该滤波器级包括动态限制器，其中动态限制器具有由过采样数据转换器的输入处的信号电平设置的限制。 过采样数据转换器还包括量化块，其包括耦合到低通滤波器的输出的输入和耦合到低通滤波器的输入的输出。