公开(公告)号：US06369397B1

公开(公告)日：2002-04-09

申请号：US09225120

申请日：1999-01-04

申请人： Brent A. Anderson ,  James A. Bruce ,  Steven J. Holmes ,  Peter H. Mitchell ,  Robert A. Myers

发明人： Brent A. Anderson ,  James A. Bruce ,  Steven J. Holmes ,  Peter H. Mitchell ,  Robert A. Myers

IPC分类号： G01N1310

CPC分类号： H01J37/3045 ,  H01J37/3174 ,  H01J2237/3175 ,  Y10S977/85

摘要： A method and apparatus for positioning a wafer in an electron beam lithography system. This method includes the steps of positioning a scanned probe microscope in the lithography system, and determining the distance between a preset location on the scanned probe microscope and a reference position in the lithography system. The wafer is brought into physical contact with that preset location, and then the wafer is moved a predetermined distance from the preset location on order to position the wafer at the desired focal plane in the lithography system.

摘要翻译： 一种用于在电子束光刻系统中定位晶片的方法和装置。 该方法包括以下步骤：将扫描的探针显微镜放置在光刻系统中，以及确定扫描的探针显微镜上的预设位置与光刻系统中的参考位置之间的距离。 将晶片与该预设位置物理接触，然后将晶片从预置位置移动预定距离，以将晶片定位在光刻系统中所需的焦平面处。

公开(公告)号：US06342735B1

公开(公告)日：2002-01-29

申请号：US09388315

申请日：1999-09-01

申请人： James J. Colelli ,  Steven J. Holmes ,  Peter H. Mitchell ,  Joseph Mundenar ,  Charles A. Whiting

发明人： James J. Colelli ,  Steven J. Holmes ,  Peter H. Mitchell ,  Joseph Mundenar ,  Charles A. Whiting

IPC分类号： H01L23544

CPC分类号： G03F9/70 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An alignment mark includes aspects of alignment marks used for two or more photolithography systems. Because the new mark includes the features specified for each system it can be read by the detectors of both systems. Since each photolithography system is substantially insensitive to the presence of the aspect used by the other system precision alignment can be achieved by each system.

摘要翻译： 对准标记包括用于两个或多个光刻系统的对准标记的方面。 因为新标记包括为每个系统指定的功能，所以可以由两个系统的检测器读取。 由于每个光刻系统对于另一个系统使用的方面的存在基本上不敏感，因此可以通过每个系统实现精确对准。

公开(公告)号：US07829883B2

公开(公告)日：2010-11-09

申请号：US10777576

申请日：2004-02-12

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 碳纳米管场效应晶体管，碳纳米管场效应晶体管阵列，器件结构和器件结构阵列。 叠层器件结构包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘。 栅电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 栅电极具有被栅极电介质覆盖的侧壁和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20100273298A1

公开(公告)日：2010-10-28

申请号：US12830510

申请日：2010-07-06

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/98

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of elongated parallel catalyst strips on a horizontal surface, and growing carbon nanotubes from the catalyst in the presence of a directional flow of reactant gases.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，定向碳纳米管通过在水平表面上形成一系列细长的平行催化剂条而形成，并且在有反应气体的定向流的存在下从催化剂生长碳纳米管。

公开(公告)号：US07566613B2

公开(公告)日：2009-07-28

申请号：US11221118

申请日：2005-09-07

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

IPC分类号： H01L21/8244

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

公开(公告)号：US20080227264A1

公开(公告)日：2008-09-18

申请号：US11926661

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/76

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

摘要翻译： 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US07229909B2

公开(公告)日：2007-06-12

申请号：US11008800

申请日：2004-12-09

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/00

CPC分类号： B82Y10/00 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

摘要翻译： 集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。 优选地，通过首先通过在表面上沉积常规电介质以填充碳纳米管之间的区域，然后通过将碳纳米管去除以形成多个相对较长的薄碳纳米管，形成集成电路晶片的表面，形成空隙 产生代替碳纳米管的空隙。 由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。 使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

公开(公告)号：US07820502B2

公开(公告)日：2010-10-26

申请号：US11926627

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaolav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaolav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/8238

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US07691720B2

公开(公告)日：2010-04-06

申请号：US11926661

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/76

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

摘要翻译： 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US07560347B2

公开(公告)日：2009-07-14

申请号：US12114180

申请日：2008-05-02

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。