公开(公告)号：US09857328B2

公开(公告)日：2018-01-02

申请号：US15239800

申请日：2016-08-17

申请人： Agilome, Inc.

发明人： Paul Hoffman

IPC分类号： H01L29/66 ,  G01N27/414 ,  H01L29/16 ,  H01L29/417 ,  G01N27/327 ,  H01L29/786

CPC分类号： G01N27/4148 ,  G01N27/3276 ,  H01L21/76879 ,  H01L21/76883 ,  H01L27/085 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/66409 ,  H01L29/78603 ,  H01L29/78684

摘要： This invention concerns chemically-sensitive field effect transistors (FETs) are preferably fabricated using semiconductor fabrication methods on a semiconductor wafer, and in preferred embodiments, on top of an integrated circuit structure made using semiconductor fabrication methods. The instant chemically-sensitive FETs typically comprise a conductive source, a conductive drain, and a channel composed of a one-dimensional (1D) or two-dimensional (2D) transistor material, which channel extends from the source to the drain and is fabricated using semiconductor fabrication techniques on top of a wafer. Such chemically-sensitive FETs, preferably configured in independently addressable arrays, may be employed to detect a presence and/or concentration changes of various analyte types in chemical and/or biological samples, including nucleic acid hybridization and/or sequencing reactions.

公开(公告)号：US09379184B1

公开(公告)日：2016-06-28

申请号：US14625062

申请日：2015-02-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Qing Cao ,  Kangguo Cheng ,  Fei Liu

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/86 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/861

CPC分类号： H01L23/544 ,  G09C1/00 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02521 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/3083 ,  H01L21/31144 ,  H01L23/576 ,  H01L29/0692 ,  H01L29/32 ,  H01L29/6609 ,  H01L29/66409 ,  H01L29/66969 ,  H01L29/772 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868 ,  H01L2223/5444 ,  H04L9/3278

摘要： A first trench having a first aspect ratio and a second trench having a second aspect ratio that is greater than the first trench are provided into a material stack of a semiconductor substrate and a dielectric material. An epitaxial semiconductor material having a different lattice constant than the substrate is then grown within each of the first and second trenches. The semiconductor material which is epitaxially formed in the first trench has an upper semiconductor material portion that is entirely defect free, while the semiconductor material which is epitaxially formed in the second trench has defects that randomly propagate to the topmost surface of the semiconductor material. At least one semiconductor device is then formed on each epitaxially grown semiconductor material. The at least one semiconductor device located on the epitaxially grown semiconductor material formed in the second trench is a physical unclonable function device.

摘要翻译： 具有第一纵横比的第一沟槽和具有大于第一沟槽的第二纵横比的第二沟槽被提供到半导体衬底和电介质材料的材料堆叠中。 然后在每个第一和第二沟槽内生长具有与衬底不同的晶格常数的外延半导体材料。 在第一沟槽中外延形成的半导体材料具有完全无缺陷的上半导体材料部分，而在第二沟槽中外延形成的半导体材料具有随机地传播到半导体材料的最上表面的缺陷。 然后在每个外延生长的半导体材料上形成至少一个半导体器件。 位于第二沟槽中形成的外延生长的半导体材料上的至少一个半导体器件是物理不可克隆功能器件。

公开(公告)号：US09287274B2

公开(公告)日：2016-03-15

申请号：US14608141

申请日：2015-01-28

申请人： SK hynix Inc.

发明人： Yeong Eui Hong

IPC分类号： H01L27/112 ,  H01L21/266 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L23/525 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/11206 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/266 ,  H01L21/28017 ,  H01L21/31105 ,  H01L23/5252 ,  H01L29/66409 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.

公开(公告)号：US08896101B2

公开(公告)日：2014-11-25

申请号：US13725546

申请日：2012-12-21

申请人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

IPC分类号： H01L29/20 ,  H01L29/772 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

摘要翻译： III-N半导体通道在过渡层和III-N偏振层之间组成分级。 在实施例中，栅堆叠沉积在包括渐变III-N半导体沟道的鳍的侧壁上，允许在响应于栅极偏置电压的至少两个侧壁表面相邻的III-N半导体沟道中形成传输沟道。 在实施例中，栅极叠层完全沉积在包括III-N半导体沟道的纳米线周围，该纳米线被组成分级，以使得能够响应于栅极形成与偏振层和过渡层两者相邻的III-N半导体沟道中的传输沟道 偏压。

公开(公告)号：US08357922B2

公开(公告)日：2013-01-22

申请号：US12866208

申请日：2008-02-05

申请人： Young-Joon Hong ,  Gyu-Chul Yi

发明人： Young-Joon Hong ,  Gyu-Chul Yi

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/2203 ,  H01L29/267 ,  H01L29/4232 ,  H01L29/66409 ,  H01L29/772 ,  H01L29/775 ,  H01L33/18

摘要： A nanodevice, a transistor including the nanodevice, a method of manufacturing the nanodevice, and a method of manufacturing the transistor including the nanodevice are provided. The nanodevice includes a substrate, a mask layer located on the substrate and having at least one opening, and a nanotube formed on the substrate through the opening along an edge of the opening. The nanotube extends through the opening in a direction substantially perpendicular to a surface of the substrate.

摘要翻译： 提供纳米器件，包括纳米器件的晶体管，制造纳米器件的方法以及制造包括纳米器件的晶体管的方法。 纳米器件包括衬底，位于衬底上并具有至少一个开口的掩模层，以及沿着开口的边缘通过开口形成在衬底上的纳米管。 纳米管沿基本上垂直于基底表面的方向延伸穿过开口。

公开(公告)号：US07820502B2

公开(公告)日：2010-10-26

申请号：US11926627

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaolav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaolav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/8238

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20080121868A1

公开(公告)日：2008-05-29

申请号：US11800914

申请日：2007-05-08

申请人： Moon-Gyu Jang ,  Yark-Yeon Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Tae-Youb Kim ,  Seong-Jae Lee

发明人： Moon-Gyu Jang ,  Yark-Yeon Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Tae-Youb Kim ,  Seong-Jae Lee

IPC分类号： H01L29/47 ,  H01L21/338

CPC分类号： H01L29/8126 ,  H01L29/66409

摘要： A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

摘要翻译： 肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。 栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。 源极和漏极区域形成在暴露于栅电极两侧的衬底中。

公开(公告)号：US09853022B2

公开(公告)日：2017-12-26

申请号：US15272499

申请日：2016-09-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC分类号： H01L21/8242 ,  H01L27/06 ,  H01L27/07 ,  H01L29/66 ,  H01L49/02 ,  H01L23/522 ,  H01L21/28 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/321

CPC分类号： H01L27/0629 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/31051 ,  H01L21/32115 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L28/88 ,  H01L29/401 ,  H01L29/66409 ,  H01L29/66545

摘要： A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

公开(公告)号：US20170102358A1

公开(公告)日：2017-04-13

申请号：US15239800

申请日：2016-08-17

申请人： Agilome, Inc.

发明人： Paul Hoffman

IPC分类号： G01N27/414 ,  H01L29/417 ,  G01N27/327 ,  H01L29/16

CPC分类号： G01N27/4148 ,  G01N27/3276 ,  H01L21/76879 ,  H01L21/76883 ,  H01L27/085 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/66409 ,  H01L29/78603 ,  H01L29/78684

摘要： This invention concerns chemically-sensitive field effect transistors (FETs) are preferably fabricated using semiconductor fabrication methods on a semiconductor wafer, and in preferred embodiments, on top of an integrated circuit structure made using semiconductor fabrication methods. The instant chemically-sensitive FETs typically comprise a conductive source, a conductive drain, and a channel composed of a one-dimensional (1D) or two-dimensional (2D) transistor material, which channel extends from the source to the drain and is fabricated using semiconductor fabrication techniques on top of a wafer. Such chemically-sensitive FETs, preferably configured in independently addressable arrays, may be employed to detect a presence and/or concentration changes of various analyte types in chemical and/or biological samples, including nucleic acid hybridization and/or sequencing reactions.

公开(公告)号：US09490252B1

公开(公告)日：2016-11-08

申请号：US14819122

申请日：2015-08-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC分类号： H01L21/8242 ,  H01L27/07 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/283 ,  H01L21/768 ,  H01L23/535

CPC分类号： H01L27/0629 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/31051 ,  H01L21/32115 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L28/88 ,  H01L29/401 ,  H01L29/66409 ,  H01L29/66545

摘要： A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

摘要翻译： 提供一种用于在替换金属栅极模块中形成金属 - 绝缘体 - 金属电容器的方法。 该方法包括提供形成在门上的栅极盖。 该方法还包括去除栅极盖的一部分并在栅极中形成凹陷。 栅极的剩余部分形成电容器的第一电极。 该方法还包括在栅极盖的剩余部分和栅极的剩余部分上沉积电介质。 该方法还包括在电介质上沉积导电材料。 该方法还包括去除导电材料的一部分和电介质的部分以暴露导电材料的剩余部分和电介质的剩余部分。 导电材料的剩余部分形成电容器的第二电极。 电介质的剩余部分形成电容器的绝缘体。