公开(公告)号：US09847398B1

公开(公告)日：2017-12-19

申请号：US15208616

申请日：2016-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/423 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; a spacer around the gate structure; a contact etch stop layer (CESL) on the spacer; an interlayer dielectric (ILD) layer adjacent to one side of the gate structure and contacting the CESL; and a contact plug adjacent to another side of the gate structure and contacting the CESL.

公开(公告)号：US09793380B2

公开(公告)日：2017-10-17

申请号：US14794821

申请日：2015-07-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.

公开(公告)号：US20170294508A1

公开(公告)日：2017-10-12

申请号：US15144842

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq ,  Tsung-Mu Yang

IPC: H01L29/06 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

公开(公告)号：US09786510B2

公开(公告)日：2017-10-10

申请号：US14512475

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L21/308 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

公开(公告)号：US09780169B2

公开(公告)日：2017-10-03

申请号：US14876844

申请日：2015-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Yu-Cheng Tung ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.

公开(公告)号：US09685385B1

公开(公告)日：2017-06-20

申请号：US15226929

申请日：2016-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L21/823821 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method for forming a semiconductor device, including the following steps: first, a substrate is provided, at least one gate is formed on the substrate, a contact etching stop layer (CESL) and a first dielectric layer are formed on the substrate in sequence, afterwards, a first etching process is performed to remove the first dielectric layer, and to expose a top surface and at least one sidewall of the etching stop layer, next, a second etching process is performed to partially remove the contact etching stop layer, and to form at least one epitaxial recess in the substrate. Afterwards, an epitaxial process is performed, to form an epitaxial layer in the epitaxial recess, and a contact structure is then formed on the epitaxial layer.

公开(公告)号：US09601600B2

公开(公告)日：2017-03-21

申请号：US14855793

申请日：2015-09-16

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Cho-Han Fan ,  Chien-Ting Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.

公开(公告)号：US20160380081A1

公开(公告)日：2016-12-29

申请号：US14818322

申请日：2015-08-05

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A FinFET includes a substrate. Numerous fin structures are defined on the substrate. A gate structure crosses each fin structure. Two epitaxial layers are disposed at two side of the gate structure, respectively. Each epitaxial layer has a top surface including a second recessed and protruding profile. A contact plug contacts the second recessed and protruding profile. The second recessed and protruding profile increases the contact area between the contact plug and the epitaxial layer.

Abstract translation: FinFET包括衬底。 在衬底上限定了许多翅片结构。 栅极结构跨越每个鳍结构。 两个外延层分别设置在栅极结构的两侧。 每个外延层具有包括第二凹入和突出轮廓的顶表面。 接触插头接触第二凹入和突出的轮廓。 第二凹入和突出的轮廓增加了接触插塞和外延层之间的接触面积。

公开(公告)号：US20160358827A1

公开(公告)日：2016-12-08

申请号：US15241077

申请日：2016-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/845 ,  H01L21/02238 ,  H01L21/02365 ,  H01L21/02367 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following step. A substrate having a first area and a second area is provided. An epitaxial structure is formed in the first area. An epitaxial structure is formed in the second area after the epitaxial structure in the first area is formed, wherein the surface area of the epitaxial structure in the first area is different from the surface area of the epitaxial structure in the second area.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域中形成外延结构。 在形成第一区域中的外延结构之后，在第二区域中形成外延结构，其中第一区域中的外延结构的表面积与第二区域中的外延结构的表面积不同。

公开(公告)号：US09443954B2

公开(公告)日：2016-09-13

申请号：US15009808

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966

Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 该方法首先包括衬底，并且在衬底上形成第一半导体器件和第二半导体器件，分别具有第一栅极沟槽和第二沟槽。 接下来，在第一栅极沟槽和第二沟槽中形成底部阻挡层。 之后，执行第一回拉步骤以去除底部阻挡层的部分，然后在第一栅极沟槽中形成第一功函数金属层。 接下来，执行第二拉回步骤以去除第一功函数金属层的部分，其中第一功函数金属层的最顶部比第一栅沟槽和第二栅沟的开口低。