公开(公告)号：US20190088639A1

公开(公告)日：2019-03-21

申请号：US15987911

申请日：2018-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L27/092 ,  H01L23/522 ,  H03K19/20 ,  H01L29/167

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

公开(公告)号：US09735235B2

公开(公告)日：2017-08-15

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/161 ,  H01L21/316 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

公开(公告)号：US20140361359A1

公开(公告)日：2014-12-11

申请号：US13914641

申请日：2013-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

IPC: H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富硅氧化物层; 和富硅氧化物层上的多晶硅层。