公开(公告)号：US20160329400A1

公开(公告)日：2016-11-10

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。

公开(公告)号：US08823141B2

公开(公告)日：2014-09-02

申请号：US13255648

申请日：2010-03-08

Applicant: Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

Inventor： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

IPC: H01L29/20 ,  H01L21/02

CPC classification number: H01L21/0237 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02642 ,  H01L29/107 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/772

Abstract: The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

Abstract translation: 半导体晶片包括：基底晶片; 以及抑制层，其一体地设置在所述基底晶片上或者彼此分离，并且抑制化合物半导体的晶体的生长，其中所述抑制层具有多个第一开口区域，所述第一开口区域具有多个 穿过所述抑制层并通向所述基底晶片的开口，所述多个第一开口区域中的每一个在其中包括设置在相同布置中的多个第一开口，所述多个第一开口中的一些是第一元件形成开口，每个元件形成开口设置有第一 其上形成有电子元件的复合半导体，并且多个第一开口中的另一个是其中不形成电子元件的第一虚拟开口。

公开(公告)号：US20140054658A1

公开(公告)日：2014-02-27

申请号：US13812499

申请日：2012-10-12

Applicant: THE INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02675 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域 其特征在于源区和漏区中的至少一个包括GeSn合金。 根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火形成GeSn应力的高浓度Sn的源区和漏极区，因此沟道区的器件载流子迁移率为 有效提高了设备​​驱动能力。

公开(公告)号：US20120025212A1

公开(公告)日：2012-02-02

申请号：US13062154

申请日：2009-09-16

Applicant: John Kouvetakis ,  Jose Menendez ,  Radek Roucka ,  Jay Mathews

Inventor： John Kouvetakis ,  Jose Menendez ,  Radek Roucka ,  Jay Mathews

IPC: H01L33/02 ,  H01L31/107 ,  H01L31/18 ,  H01L31/102

CPC classification number: H01L31/107 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/0257 ,  H01L27/14649 ,  H01L31/03125 ,  H01L31/075

Abstract: Photodiode devices with GeSn active layers can be integrated directly on p+ Si platforms under CMOS-compatible conditions. It has been found that even minor amounts of Sn incorporation (2%) dramatically expand the range of IR detection up to at least 1750 nm and substantially increases the absorption. The corresponding photoresponse can cover of all telecommunication bands using entirely group IV materials.

Abstract translation: 具有GeSn有源层的光电二极管器件可以在CMOS兼容条件下直接集成到p + Si平台上。 已经发现，甚至少量的Sn掺入（2％）显着地将IR检测的范围扩大到至少1750nm，并且显着增加了吸收。 相应的光响应可以覆盖所有使用完全IV组材料的电信频段。

公开(公告)号：US07582891B2

公开(公告)日：2009-09-01

申请号：US11663024

申请日：2005-09-16

Applicant: John Kouvetakis ,  Jose Menendez ,  John Tolle ,  Ling Liao ,  Dean Samara-Rubio

Inventor： John Kouvetakis ,  Jose Menendez ,  John Tolle ,  Ling Liao ,  Dean Samara-Rubio

IPC: H01L29/739

CPC classification number: G02F1/017 ,  B82Y20/00 ,  G02F1/01708 ,  G02F2001/0157 ,  G02F2203/11 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/0262 ,  H01L31/028 ,  H01L31/035254 ,  H01L31/109 ,  Y02E10/547

Abstract: Semiconductor structures having at least one quantum well heterostructure grown strain-free on Si(100) via a Sn1-xGex buffer layer and their uses are provided.

Abstract translation: 提供了具有通过Sn1-xGex缓冲层在Si（100）上生长无应变的至少一个量子阱异质结的半导体结构及其用途。

公开(公告)号：US4670293A

公开(公告)日：1987-06-02

申请号：US899789

申请日：1986-08-22

Applicant: Masaru Yamano ,  Yukinori Kuwano ,  Shoichi Nakano ,  Tsugufumi Matsuoka ,  Souichi Sakai ,  Hirosato Yagi ,  Nobuhiro Okuda

Inventor： Masaru Yamano ,  Yukinori Kuwano ,  Shoichi Nakano ,  Tsugufumi Matsuoka ,  Souichi Sakai ,  Hirosato Yagi ,  Nobuhiro Okuda

IPC: E04D13/18 ,  H01L21/205 ,  H01L27/142 ,  H01L31/0392 ,  H01L31/048 ,  H01L31/20 ,  B05D3/06

CPC classification number: H01L31/202 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L31/03921 ,  H01L31/046 ,  H01L31/0463 ,  H02S20/25 ,  Y02B10/12 ,  Y02E10/50 ,  Y02P70/521 ,  Y10S136/291

Abstract: A method of making a semiconductor film on a substrate having a non-flat surface, by placing the substrate in a reaction chamber including at least a pair of discharge electrodes, an inlet of a reaction gas for producing a desired semiconductor film, and an outlet for reduced pressure, and performing a discharge in the presence of said reacrion gas for producing said semiconductor film, while arranging said non-flat surface of said substrate outside a plasma region formed between said discharge electrodes and further locating said non-flat surface substantially in a vertical direction with respect to electrode surfaces of said discharge electrodes, thereby semiconductor film being directly and uniformly deposited on said non-flat surface of said substrate, which is of worth in the production of, e.g., roofing tile-shaped photovoltaic devices.

Abstract translation: 通过将基板放置在包括至少一对放电电极的反应室，用于制造期望的半导体膜的反应气体的入口和出口的方法，在具有非平坦表面的基板上制造半导体膜的方法 为了减压，在存在用于制造所述半导体膜的所述反应气体的情况下进行放电，同时将所述衬底的所述非平坦表面布置在形成在所述放电电极之间的等离子体区域的外部，并进一步将所述非平坦表面定位在基本上 相对于所述放电电极的电极表面的垂直方向，由此半导体膜直接且均匀地沉积在所述基板的所述非平坦表面上，这在制造例如屋顶瓦片状光伏器件中是有价值的。

公开(公告)号：US20170372884A1

公开(公告)日：2017-12-28

申请号：US15627189

申请日：2017-06-19

Applicant: ASM IP Holding B.V.

Inventor： Joe Margetis ,  John Tolle

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/768

CPC classification number: H01L21/02005 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/0262 ,  H01L21/67167 ,  H01L21/7688 ,  H01L29/161

Abstract: A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.

公开(公告)号：US09735235B2

公开(公告)日：2017-08-15

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/161 ,  H01L21/316 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

公开(公告)号：US20160071921A1

公开(公告)日：2016-03-10

申请号：US14928341

申请日：2015-10-30

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masahiro KOIKE ,  Yuuichi KAMIMUTA ,  Tsutomu TEZUKA

IPC: H01L29/04 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/28052 ,  H01L21/2807 ,  H01L21/28518 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/78

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including Ge; and a metal Ge compound region provided in a surface portion of the semiconductor layer. Sn is included in an interface portion between the semiconductor layer and the metal Ge compound region. A lattice plane of the semiconductor layer matches with a lattice plane of the metal Ge compound region.

Abstract translation: 根据一个实施例，半导体器件包括包含Ge的半导体层; 以及设置在半导体层的表面部分中的金属Ge化合物区域。 Sn被包括在半导体层和金属Ge化合物区域之间的界面部分中。 半导体层的晶格面与金属Ge化合物区域的晶格面匹配。

公开(公告)号：US20150332921A1

公开(公告)日：2015-11-19

申请号：US14483169

申请日：2014-09-11

Applicant: NATIONAL TSING HUA UNIVERSITY

Inventor： Ming-Chang LEE ,  Chih-Kuo TSENG

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L21/02667 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02642 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/36

Abstract: The present disclosure provides a carrier channel with an element concentration gradient distribution. The carrier channel includes a substrate and a carrier channel structure. The carrier channel structure is stacked on the substrate, wherein a ratio of a height and a width of the carrier channel is greater than 1, and the carrier channel is crystallized from the contact surface by a rapid melting growth process, thus the carrier channel structure has the element concentration gradient distribution.

Abstract translation: 本公开提供了具有元素浓度梯度分布的载波信道。 载体通道包括基底和载体通道结构。 载体沟道结构层叠在基板上，其中载流子通道的高度和宽度的比率大于1，并且通过快速熔融生长工艺从载体通道从接触表面结晶，因此载流子通道结构 具有元素浓度梯度分布。