公开(公告)号：US20190206724A1

公开(公告)日：2019-07-04

申请号：US16003126

申请日：2018-06-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Hsin-Yu Chiang ,  Yu-Ching Chen

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76805 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76897

Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.

公开(公告)号：US20190157274A1

公开(公告)日：2019-05-23

申请号：US15841257

申请日：2017-12-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chun-Hsien Lin ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/49

CPC classification number: H01L27/10823 ,  H01L21/0214 ,  H01L27/10876 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/4991 ,  H01L29/518

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

公开(公告)号：US20190013321A1

公开(公告)日：2019-01-10

申请号：US15990811

申请日：2018-05-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Ching Chang ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  G11C11/401

Abstract: A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.

公开(公告)号：US10153165B1

公开(公告)日：2018-12-11

申请号：US15868915

申请日：2018-01-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Chien-Cheng Tsai

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/027

Abstract: The present invention pertains to a patterning method. By taking advantage of the etching loading effect due to different pattern densities in the memory cell region and the peripheral region, the first hard mask is not masked when anisotropically etching the first hard mask within the memory cell region.

公开(公告)号：US20180315759A1

公开(公告)日：2018-11-01

申请号：US15920468

申请日：2018-03-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Liang Liao ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Yi-Wang Zhan

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/535

Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

公开(公告)号：US20180286871A1

公开(公告)日：2018-10-04

申请号：US15925778

申请日：2018-03-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10894 ,  H01L21/7682 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

Abstract: The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.

公开(公告)号：US20180286867A1

公开(公告)日：2018-10-04

申请号：US15937849

申请日：2018-03-27

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer. Then, a stacked structure is formed on the dielectric layer, and the stacked structure includes a first layer, a second layer and a third layer stacked one over another on the conductive pad. Next, a patterned mask layer is formed on the stacked structure, and a portion of the stacked structure is removed, to form an opening in the stacked structure, with the opening having a taped sidewall in the second layer and the first layer. After that, the taped sidewall of the opening in the second layer is vertically etched, to form a contact opening in the stacked structure. Finally, the patterned mask layer is removed.

公开(公告)号：US20180197863A1

公开(公告)日：2018-07-12

申请号：US15859763

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/033 ,  H01L49/02 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L27/1085 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.

公开(公告)号：US20180190663A1

公开(公告)日：2018-07-05

申请号：US15458946

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang ,  Hsien-Shih Chu

IPC: H01L27/108

CPC classification number: H01L27/1085 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10847 ,  H01L27/10882 ,  H01L27/10888

Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.

公开(公告)号：US20180190657A1

公开(公告)日：2018-07-05

申请号：US15856084

申请日：2017-12-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/91

Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.