公开(公告)号：US10373872B2

公开(公告)日：2019-08-06

申请号：US15813945

申请日：2017-11-15

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US20190115260A1

公开(公告)日：2019-04-18

申请号：US15813945

申请日：2017-11-15

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/49

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L21/8249 ,  H01L27/0251 ,  H01L29/0607 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/78 ,  H01L29/7832 ,  H01L29/7835

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US20180233416A1

公开(公告)日：2018-08-16

申请号：US15953537

申请日：2018-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/823481 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31105 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/401 ,  H01L29/4966

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

公开(公告)号：US09985129B2

公开(公告)日：2018-05-29

申请号：US15820467

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/033

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US09859417B2

公开(公告)日：2018-01-02

申请号：US15191535

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US20170345926A1

公开(公告)日：2017-11-30

申请号：US15191535

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US20170047397A1

公开(公告)日：2017-02-16

申请号：US14859348

申请日：2015-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/7836

Abstract: A method for fabricating isolation device is disclosed. The method includes the steps of: providing a substrate; forming a shallow trench isolation (STI) in the substrate, the STI includes a first STI and a second STI, and the first STI surrounds a first device region and the second STI surrounds a second device region; forming a first doped region between and contact the first STI and the second STI; and forming a first gate structure on the first doped region, the first STI and the second STI.

Abstract translation: 公开了一种用于制造隔离装置的方法。 该方法包括以下步骤：提供衬底; 在衬底中形成浅沟槽隔离（STI），STI包括第一STI和第二STI，并且第一STI围绕第一器件区域，第二STI围绕第二器件区域; 在第一STI和第二STI之间形成第一掺杂区域并接触第一STI; 以及在所述第一掺杂区域上形成第一栅极结构，所述第一STI和所述第二STI。