公开(公告)号：US11955519B2

公开(公告)日：2024-04-09

申请号：US18135206

申请日：2023-04-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

CPC classification number: H01L29/151 ,  H01L29/7786

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US11557666B2

公开(公告)日：2023-01-17

申请号：US17100935

申请日：2020-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/00 ,  H01L29/778 ,  H01L21/768 ,  H01L21/67 ,  H01L29/66

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

公开(公告)号：US11508818B2

公开(公告)日：2022-11-22

申请号：US17506685

申请日：2021-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US20220310794A1

公开(公告)日：2022-09-29

申请号：US17685400

申请日：2022-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US11257939B2

公开(公告)日：2022-02-22

申请号：US16711451

申请日：2019-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Yu-Chi Wang ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.

公开(公告)号：US10236179B2

公开(公告)日：2019-03-19

申请号：US15099581

申请日：2016-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Cheng Yen ,  Tsung-Mu Yang ,  Sheng-Hsu Liu ,  Tsang-Hsuan Wang ,  Chun-Liang Kuo ,  Yu-Ming Hsu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

公开(公告)号：US20170301536A1

公开(公告)日：2017-10-19

申请号：US15099581

申请日：2016-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Cheng Yen ,  Tsung-Mu Yang ,  Sheng-Hsu Liu ,  Tsang-Hsuan Wang ,  Chun-Liang Kuo ,  Yu-Ming Hsu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/0262 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02639 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

公开(公告)号：US09214551B2

公开(公告)日：2015-12-15

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US20150236158A1

公开(公告)日：2015-08-20

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US12224339B2

公开(公告)日：2025-02-11

申请号：US17735100

申请日：2022-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.