公开(公告)号：US10276710B1

公开(公告)日：2019-04-30

申请号：US15965267

申请日：2018-04-27

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: A high voltage transistor including a substrate is provided, and the substrate has an indent region. A doped region is disposed in the substrate at both sides of the indent region. A shallow trench isolation (STI) structure is disposed in the doped region of the substrate, at a periphery region of the indent region, wherein a portion of a bottom of the STI structure within the indent region has a protruding part down into the substrate. A gate insulating layer is disposed on the substrate at a central region of the indent region other than the STI structure, wherein the gate insulating layer has a protruding portion. A gate structure is disposed on the gate insulating layer and the STI structure within the indent region, covering the protruding portion of the gate insulating layer.

公开(公告)号：US20180102408A1

公开(公告)日：2018-04-12

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US12206020B2

公开(公告)日：2025-01-21

申请号：US18139964

申请日：2023-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US11437512B2

公开(公告)日：2022-09-06

申请号：US16934030

申请日：2020-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung

IPC: H01L29/78 ,  H01L21/8238

Abstract: A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a “-” shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET.

公开(公告)号：US20220209009A1

公开(公告)日：2022-06-30

申请号：US17159166

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US20210167208A1

公开(公告)日：2021-06-03

申请号：US16711442

申请日：2019-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Shin-Hung Li

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

公开(公告)号：US10453938B2

公开(公告)日：2019-10-22

申请号：US15846150

申请日：2017-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US20190103460A1

公开(公告)日：2019-04-04

申请号：US15720204

申请日：2017-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Chia-Lin Wang ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor transistor device is provided. The semiconductor transistor device includes a semiconductor substrate, a gate structure, a first isolation structure, a first doped region, and a first extra-contact structure. The gate structure is disposed on the semiconductor substrate, and the semiconductor substrate has a first region and a second region respectively located on two opposite sides of the gate structure. The first isolation structure and the first doped region are disposed in the first region of the semiconductor substrate. The first extra-contact structure is disposed on the semiconductor structure. The first extra-contact structure is located between the gate structure and the first doped region and penetrating into the first isolation structure in the first region of the semiconductor substrate, and the first doped region is electrically coupled to the first extra-contact structure.

公开(公告)号：US09972678B2

公开(公告)日：2018-05-15

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US09653343B1

公开(公告)日：2017-05-16

申请号：US15172136

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao ,  Chang-Po Hsiung

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/76235 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42364

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.