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    METHOD FOR FORMING SEMICONDUCTOR DEVICE
    21.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200020576A1

    公开(公告)日：2020-01-16

    申请号：US16033179

    申请日：2018-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

    IPC: H01L21/768 ,  H01L21/47 ,  H01L21/02

    Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.

    Patterning method
    22.
    发明授权
    Patterning method 有权

    公开(公告)号：US10373829B1

    公开(公告)日：2019-08-06

    申请号：US16052625

    申请日：2018-08-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tsung-Yin Hsieh ,  Chih-Sheng Chang

    IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

    Abstract: A patterning method includes the following steps. A layout pattern is provided to a computer system. The layout pattern includes stripe patterns, and each of the stripe patterns extends in a first direction. Mandrel patterns are formed corresponding to a part of the stripe patterns. Each of the mandrel patterns extends in the first direction. A modification is performed to the mandrel patterns for elongating at least a part of the mandrel patterns in the first direction. Ends of the mandrel patterns in the first direction are aligned in a second direction perpendicular to the first direction after the modification. The mandrel patterns are outputted to a photomask after the modification. A photolithography process using the photomask is performed for forming a patterned structure on a substrate. By performing the modification to the mandrel patterns, design flexibility of the layout pattern corresponding to the patterning method may be enhanced.

    Metal-insulator-metal capacitor and method for fabricating the same
    26.
    发明授权
    Metal-insulator-metal capacitor and method for fabricating the same 有权

    公开(公告)号：US11469294B2

    公开(公告)日：2022-10-11

    申请号：US16862827

    申请日：2020-04-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Bo-Wei Huang ,  Chun-Wei Kang ,  Ho-Yu Lai ,  Chih-Sheng Chang

    IPC: H01L49/02 ,  H01L23/64

    Abstract: A metal-insulator-metal (MIM) capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substrate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

    Semiconductor structure with super via and manufacturing method thereof
    27.
    发明申请
    Semiconductor structure with super via and manufacturing method thereof 有权

    公开(公告)号：US20220216144A1

    公开(公告)日：2022-07-07

    申请号：US17168099

    申请日：2021-02-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

    IPC: H01L23/522 ,  H01L21/768 ,  H01L21/033 ,  H01L23/528

    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.

    Forming contact holes using litho-etch-litho-etch approach
    28.
    发明授权
    Forming contact holes using litho-etch-litho-etch approach 有权

    公开(公告)号：US10916427B2

    公开(公告)日：2021-02-09

    申请号：US16033179

    申请日：2018-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

    IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/47

    Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.

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