公开(公告)号：US20240404587A1

公开(公告)日：2024-12-05

申请号：US18218025

申请日：2023-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: G11C11/412 ,  G11C5/06

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

公开(公告)号：US12148809B2

公开(公告)日：2024-11-19

申请号：US17583225

申请日：2022-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US20230403837A1

公开(公告)日：2023-12-14

申请号：US17857065

申请日：2022-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L27/11

CPC classification number: H01L27/1104

Abstract: The invention provides a static random access memory (SRAM) array pattern, which comprises a substrate, a first region, a second region, a third region and a fourth region are defined on the substrate and arranged in an array, each region partially overlaps with the other three regions, and each region contains a SRAM cell, the layout of the SRAM cell in the first region is the same as that in the third region, the layout of the SRAM cell in the second region is the same as that in the fourth region, and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis.

公开(公告)号：US20230018513A1

公开(公告)日：2023-01-19

申请号：US17952327

申请日：2022-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H01L27/22 ,  H01L43/02

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

公开(公告)号：US20210118507A1

公开(公告)日：2021-04-22

申请号：US17114373

申请日：2020-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng

IPC: G11C15/04 ,  H01L27/02 ,  H01L27/11

Abstract: A layout pattern of a two-port ternary content addressable memory (TCAM) includes a first storage unit, a second storage unit, a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit are positioned in a first side area of a side and a second side area of another side of the layout pattern, respectively. The first storage unit and the second storage unit are positioned in a first middle area and a second middle area between the first side area and the second side area, respectively. The first storage unit is connected to the first comparison circuit through a first gate structure and connected to the second comparison circuit through a second gate structure. The second storage unit is connected to the first comparison circuit through a third gate structure and connected to the second comparison circuit through a fourth gate structure.

公开(公告)号：US10762951B1

公开(公告)日：2020-09-01

申请号：US16455783

申请日：2019-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Tsai ,  Tsan-Tang Chen ,  Chung-Cheng Tsai ,  Yen-Hsueh Huang ,  Chang-Ting Lo ,  Chun-Yen Tseng ,  Yu-Tse Kuo

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.

公开(公告)号：US10706914B2

公开(公告)日：2020-07-07

申请号：US16019521

申请日：2018-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Shu-Ru Wang

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L43/08 ,  G11C7/12 ,  H01L27/11 ,  H01L43/02 ,  H01L43/10 ,  G01R33/09 ,  G11C8/08

Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.

公开(公告)号：US20200083232A1

公开(公告)日：2020-03-12

申请号：US16152423

申请日：2018-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78

Abstract: A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL1) and a gate of a first pull-down device (PD1). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL2) and a gate of a second pull-down device (PD2) and the gate of the PD1 is directly under the gate of the PD2.

公开(公告)号：US20190362776A1

公开(公告)日：2019-11-28

申请号：US16019521

申请日：2018-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Shu-Ru Wang

IPC: G11C11/412 ,  G11C11/419 ,  H01L43/08 ,  G11C7/12 ,  G11C8/08 ,  H01L43/02 ,  H01L43/10 ,  G01R33/09 ,  H01L27/11

Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.

公开(公告)号：US20190206879A1

公开(公告)日：2019-07-04

申请号：US15884063

申请日：2018-01-30

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Shu-Ru Wang ,  Wei-Chi Lee ,  Chun-Yen Tseng

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/41 ,  H01L23/522 ,  H01L27/02

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.