公开(公告)号：US11706933B2

公开(公告)日：2023-07-18

申请号：US17224140

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang ,  Chung-Tse Chen

IPC: H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/80 ,  H10B63/30 ,  H10N70/041 ,  H10N70/24 ,  H10N70/8833

Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

公开(公告)号：US11706915B2

公开(公告)日：2023-07-18

申请号：US17381219

申请日：2021-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7881

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

公开(公告)号：US20220406800A1

公开(公告)日：2022-12-22

申请号：US17381219

申请日：2021-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

公开(公告)号：US10770565B2

公开(公告)日：2020-09-08

申请号：US16123868

申请日：2018-09-06

Applicant: United Microelectronics Corp.

Inventor： Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chuan-Fu Wang ,  Yu-Huang Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/45 ,  H01L29/49

Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

公开(公告)号：US10312250B1

公开(公告)日：2019-06-04

申请号：US15878278

申请日：2018-01-23

Applicant: United Microelectronics Corp.

Inventor： Hsuan-Chun Tseng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chi-Cheng Huang ,  Ping-Chia Shih

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L27/11578

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.

公开(公告)号：US10074692B2

公开(公告)日：2018-09-11

申请号：US15884827

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H05K999/99

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

公开(公告)号：US09691671B2

公开(公告)日：2017-06-27

申请号：US14472348

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tse-Min Chao ,  Tzu-Yun Chang ,  Hsueh-Chun Hsiao

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern.

公开(公告)号：US20160064295A1

公开(公告)日：2016-03-03

申请号：US14472348

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tse-Min Chao ,  Tzu-Yun Chang ,  Hsueh-Chun Hsiao

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern.

Abstract translation: 本发明提供了包括下导电图案的测试键阵列，并且下导电图案包括彼此平行的多个第一L形迹线，上导电图案，其中上导电图案包括多个第二L形迹线， 形状的迹线彼此平行，下导电图案与上导电图案交叉，并且在下导电图案和上导电图案之间限定多个交叉区域，以及多个导电插头，设置在十字的部分上 区域，电连接到下导电图案和上导电图案。