公开(公告)号：US10790365B2

公开(公告)日：2020-09-29

申请号：US15903709

申请日：2018-02-23

Applicant: Vanguard International Semiconductor Corporation

Inventor： Wen-Hsin Lin ,  Yu-Hao Ho ,  Shin-Cheng Lin ,  Cheng-Tsung Wu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/423

Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.

公开(公告)号：US10355096B2

公开(公告)日：2019-07-16

申请号：US16107058

申请日：2018-08-21

Applicant: Vanguard International Semiconductor Corporation

Inventor： Hsin-Chih Lin ,  Shin-Cheng Lin ,  Yung-Hao Lin

IPC: H01L21/84 ,  H01L29/423 ,  H01L29/778 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417 ,  H01L29/36 ,  H01L29/20

Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.

公开(公告)号：US10256332B1

公开(公告)日：2019-04-09

申请号：US15795526

申请日：2017-10-27

Applicant: Vanguard International Semiconductor Corporation

Inventor： Fu-Hsin Chen ,  Yung-Hao Lin ,  Shin-Cheng Lin ,  Hsin-Chih Lin ,  Chia-Ching Huang

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/207 ,  H01L29/423 ,  H01L23/31 ,  H01L29/66 ,  H01L23/29

Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.

公开(公告)号：US10217831B1

公开(公告)日：2019-02-26

申请号：US15692516

申请日：2017-08-31

Applicant: Vanguard International Semiconductor Corporation

Inventor： Hsin-Chih Lin ,  Shin-Cheng Lin ,  Yung-Hao Lin

IPC: H01L29/66 ,  H01L29/36 ,  H01L29/423 ,  H01L29/778 ,  H01L21/265

Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.

公开(公告)号：US10205014B2

公开(公告)日：2019-02-12

申请号：US15377590

申请日：2016-12-13

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shang-Hui Tu ,  Chih-Jen Huang ,  Jui-Chun Chang ,  Shin-Cheng Lin ,  Yu-Hao Ho ,  Wen-Hsin Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L21/70 ,  H01L21/265 ,  H01L21/266 ,  H01L29/423

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

公开(公告)号：US10128331B1

公开(公告)日：2018-11-13

申请号：US15666098

申请日：2017-08-01

Applicant: Vanguard International Semiconductor Corporation

Inventor： Cheng-Tsung Wu ,  Shin-Cheng Lin ,  Wen-Hsin Lin ,  Yu-Hao Ho

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/761

Abstract: A high-voltage semiconductor device is provided. The device includes an epitaxial layer formed on a semiconductor substrate. The semiconductor substrate includes a first doping region having a first conductivity type. The epitaxial layer includes a body region that has a second conductivity type and a second doping region and a third doping region that have the first conductivity type. The second doping region and the third doping region are respectively on both opposite sides of the body region. A source region and a drain region are respectively in the body region and the second doping region. A gate structure is on the epitaxial layer. A fourth doping region having the second conductivity region is below the source region and adjacent to the bottom of the body region. The fourth doping region has a doping concentration greater than that of the body region.

公开(公告)号：US09799512B1

公开(公告)日：2017-10-24

申请号：US15361140

申请日：2016-11-25

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yu-Lung Chin ,  Shin-Cheng Lin

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/32

CPC classification number: H01L21/0254 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02639 ,  H01L21/02645 ,  H01L33/00

Abstract: A semiconductor substrate structure includes a seed layer on a substrate, a first gallium nitride layer on the seed layer, and a patterned first hard mask layer on the first gallium nitride layer, wherein the patterned first hard mask layer includes a first opening. The semiconductor substrate structure also includes a second gallium nitride layer in the first opening and on the patterned first hard mask layer, a patterned second hard mask layer on the second gallium nitride layer, wherein the patterned second hard mask layer includes a second opening, and at least a portion of a projection on the substrate of the first opening and a projection on the substrate of the second opening are non-overlapped. The semiconductor substrate structure further includes a third gallium nitride layer in the second opening and on the patterned second hard mask layer.

公开(公告)号：US20170213898A1

公开(公告)日：2017-07-27

申请号：US15430097

申请日：2017-02-10

Applicant: Vanguard International Semiconductor Corporation

Inventor： Tsung-Hsiung Lee ,  Shin-Cheng Lin

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/36

CPC classification number: H01L29/66659 ,  H01L21/265 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

公开(公告)号：US09553143B2

公开(公告)日：2017-01-24

申请号：US14620993

申请日：2015-02-12

Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

Inventor： Shang-Hui Tu ,  Yu-Lung Chin ,  Shin-Cheng Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure.

Abstract translation: 半导体器件包括：半导体衬底; 设置在所述半导体层上的半导体层; 布置在半导体层和半导体衬底中的第一阱区; 布置在所述半导体层中的第二阱区; 设置在第一阱区中的第一隔离元件; 设置在第二阱区中的第二隔离元件; 设置在第一隔离元件和第二隔离元件之间的半导体层中的栅极结构; 设置在所述第一阱区中的第一掺杂区; 以及设置在第二阱区中的第二掺杂区。 栅极结构的底表面在第一隔离结构的底表面的上方，下方或基本上平齐。

公开(公告)号：US09306034B2

公开(公告)日：2016-04-05

申请号：US14187950

申请日：2014-02-24

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shang-Hui Tu ,  Chih-Jen Huang ,  Jui-Chun Chang ,  Shin-Cheng Lin ,  Yu-Hao Ho ,  Wen-Hsin Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/70

CPC classification number: H01L29/7801 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract translation: 提供半导体器件。 该器件包括具有第一导电类型的衬底。 该器件还包括漏极区域，源极区域和设置在衬底中的阱区域。 阱区域设置在漏极区域和源极区域之间并且具有与第一导电类型相反的第二导电类型。 该器件还包括设置在阱区内的多个掺杂区域。 掺杂区域彼此垂直和水平地偏移。 每个掺杂区域包括具有第一导电类型的下部分和堆叠在下部区域上并具有第二导电类型的上部。