公开(公告)号：US5410680A

公开(公告)日：1995-04-25

申请号：US153696

申请日：1993-11-17

申请人： Nagesh Challa ,  Michel E. Gannage

发明人： Nagesh Challa ,  Michel E. Gannage

IPC分类号： G06F3/06 ,  G11C7/10 ,  G06F12/00

CPC分类号： G06F3/0601 ,  G11C7/1075 ,  G06F2003/0694

摘要： A magnetic media hard disk is emulated in a solid state hard disk having a disk controller, a data buffer, a microcontroller, and a disk emulator section. The disk emulator section includes a disk emulator interface and a memory array. The architecture of the memory array includes a number of memory banks which typically correspond to respective sectors of the emulated hard disk, but could correspond to respective groups of sectors of the emulated hard disk. Each of the memory banks has its own serial data line and its own serial clock line, and include a number of serial memory devices that connect to the bank serial data line and bank clock line with respective serial data and clock lines. Each of the serial memory devices also has a static address corresponding to a head address of the emulated hard disk. At any given time, one of the memory banks is selected by activation of its clock line based on the sector addressed, and one of the serial memory devices in the bank responds based on a comparison of its static address with head address data communicated on the serial data line. Other features described include serial memory device start sequences and bad bit replacement.

摘要翻译： 在具有盘控制器，数据缓冲器，微控制器和磁盘仿真器部分的固态硬盘中模拟磁性介质硬盘。 磁盘仿真器部分包括磁盘仿真器接口和存储器阵列。 存储器阵列的架构包括通常对应于仿真硬盘的相应扇区的多个存储器组，但是可对应于模拟硬盘的相应扇区组。 每个存储体都有自己的串行数据线和自己的串行时钟线，并且包括连接到具有相应串行数据和时钟线的存储体串行数据线和存储体时钟线的多个串行存储器件。 每个串行存储器设备还具有与仿真硬盘的头地址对应的静态地址。 在任何给定时间，通过基于所寻址的扇区激活其时钟线来选择存储体之一，并且存储体中的一个串行存储器件基于其静态地址与在 串行数据线。 所描述的其他功能包括串行存储器设备启动序列和坏位替换。

公开(公告)号：US5508955A

公开(公告)日：1996-04-16

申请号：US64531

申请日：1993-05-20

申请人： Jan Zimmer ,  Nagesh Challa

发明人： Jan Zimmer ,  Nagesh Challa

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L29/7883 ,  G11C16/0491 ,  H01L27/115

摘要： A memory cell (510) suitable for an array of memory cells (100) has a source that is part of a buried bit line and a drain that is part of an adjacent buried bit line. The memory cell also includes a split gate arrangement (580) in which the gate is integral with the word line (120), with a part of the gate being the control gate of an EEPROM transistor which erases and programs on the principle of Fowler-Nordheim tunneling (560, 570), and another part of the gate being the control gate of a series select transistor. The memory cell is erased by placing a voltage on the word line which is positive relative to the bit line and the substrate and of sufficient magnitude to cause tunneling. The memory cell is programmed by placing a negative voltage on the word line and a voltage corresponding to the logical value on the bit line. The bit line voltage is sufficient to cause tunneling for one logical value, and insufficient to cause tunneling for the other logical value. The memory cell is read by placing a sense voltage across the bit lines forming its source and drain, and a read voltage on the control gate. Other bit lines are left floating.

摘要翻译： 适合于存储单元阵列（100）的存储单元（510）具有作为相邻掩埋位线的一部分的掩埋位线和漏极的一部分的源极。 存储单元还包括分​​离栅极布置（580），其中栅极与字线（120）成一体，栅极的一部分是EEPROM晶体管的控制栅极，其基于Fowler- Nordheim隧道（560,570），栅极的另一部分是串联选择晶体管的控制栅极。 通过在字线上放置一个电压来消除存储单元，该电压相对于位线和衬底是正的，并且具有足够的量级以引起隧道。 通过在字线上放置负电压并对应于位线上的逻辑值的电压对存储单元进行编程。 位线电压足以导致一个逻辑值的隧道，并且不足以导致另一个逻辑值的隧道。 通过在形成其源极和漏极的位线之间放置感测电压以及控制栅极上的读取电压来读取存储器单元。 其他位线保持浮动。

公开(公告)号：US5408431A

公开(公告)日：1995-04-18

申请号：US258050

申请日：1994-06-10

申请人： Nagesh Challa

发明人： Nagesh Challa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/26

摘要： A single-transistor EEPROM device of the present invention comprises memory transistors in banks similar to NAND structures wherein the control gates of the memory transistors have negative voltages applied in various modes that allow reading, writing, and programming regardless of the V.sub.th of nonselected memory transistors in a bank. Programming and erasing results from various combinations of negative and positive voltages are used on the select gates together with positive voltages less than that alone which is necessary to induce Fowler-Nordheim tunneling are applied to the bit lines.

摘要翻译： 本发明的单晶体管EEPROM器件包括类似于NAND结构的存储器晶体管，其中存储晶体管的控制栅极具有以允许读取，写入和编程的各种模式施加的负电压，而与无选择的存储器晶体管的Vth无关。 在银行里。 在选择栅极上使用来自负电压和正电压的各种组合的编程和擦除结果，以及仅将诱导Fowler-Nordheim隧道施加到位线所需的正电压。

公开(公告)号：US5297081A

公开(公告)日：1994-03-22

申请号：US896772

申请日：1992-06-10

申请人： Nagesh Challa

发明人： Nagesh Challa

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C11/40

CPC分类号： G11C16/26 ,  G11C16/0416 ,  G11C16/08

摘要： A memory (1) operative in an erase mode, a program mode, or a read mode includes a memory cell array, word lines (30, 40, 50, 60), a row decoder (9) connected to the word lines, bit lines (2, 4, 6, 8), a precharge circuit (70, 72, 74, 76, 78, 80) connected to the bit lines, a load circuit (22, 23, 24, 25, 26, 27, 28, 29) connected to the bit lines, and a sense circuit (12, 14, 16, 18) connected to the bit lines. The memory array includes both floating gate MOSFET transistors and switch MOSFET transistors arranged in groups associated with respective subsets of word lines and bit lines. Within each group, the sources of the floating gate transistors (32, 34, 42, 44) and switch transistors (35, 45) are commonly connected, the control gates and drains of the floating gate transistors are respectively connected to a unique associated word line (30, 40)--associated bit line (2, 4) pair, and each of the switch transistors has its gate connected to a unique associated word line and its drain connected to a reference line (5). The sense current threshold is set between an amount of current drawn by one ON floating gate transistor and an amount of current drawn by a number of OFF floating gate transistors equal to the number of floating gate transistors within a group connected to a single bit line, minus one.

摘要翻译： 以擦除模式，程序模式或读取模式操作的存储器（1）包括存储单元阵列，字线（30,40,50,60），连接到字线的行解码器（9），位 线路（2,4,6,8），连接到位线的预充电电路（70,72,74,76,78,80），负载电路（22,23,24,25,26,27,28） ，29）和连接到所述位线的感测电路（12,14,16,18）。 存储器阵列包括浮置栅极MOSFET晶体管和以与字线和位线的相应子集相关联的组的开关MOSFET晶体管。 在每组中，浮动栅晶体管（32,34,42,44）和开关晶体管（35,45）的源极共同连接，浮栅晶体管的控制栅极和漏极分别连接到唯一的相关字 （30,40）相关的位线（2,4）对，并且每个开关晶体管的栅极连接到唯一的相关联的字线，并且其漏极连接到参考线（5）。 感测电流阈值被设置在由一个ON浮栅晶体管汲取的电流量与等于连接到单个位线的组中的浮栅晶体管的数量的多个OFF浮栅晶体管汲取的电流量之间， 减一。

公开(公告)号：US5414658A

公开(公告)日：1995-05-09

申请号：US245189

申请日：1994-05-17

申请人： Nagesh Challa

发明人： Nagesh Challa

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C13/00

CPC分类号： G11C16/26 ,  G11C16/0416 ,  G11C16/08

摘要： A memory (1) operative in an erase mode, a program mode, or a read mode includes a memory cell array, word lines (30, 40, 50, 60), a row decoder (9) connected to the word lines, bit lines (2, 4, 6, 8), a precharge circuit (70, 72, 74, 76, 78, 80) connected to the bit lines, a load circuit (22, 23, 24, 25, 26, 27, 28, 29) connected to the bit lines, and a sense circuit (12, 14, 16, 18) connected to the bit lines. The memory array includes both floating gate MOSFET transistors and switch MOSFET transistors arranged in groups associated with respective subsets of word lines and bit lines. Within each group, the sources of the floating gate transistors (32, 34, 42, 44) and switch transistors (35, 45) are commonly connected, the control gates and drains of the floating gate transistors are respectively connected to a unique associated word line (30, 40)--associated bit line (2, 4) pair, and each of the switch transistors has its gate connected to a unique associated word line and its drain connected to a reference line (5). The sense current threshold is set between an amount of current drawn by one ON floating gate transistor and an amount of current drawn by a number of OFF floating gate transistors equal to the number of floating gate transistors within a group connected to a single bit line, minus one.

摘要翻译： 以擦除模式，程序模式或读取模式操作的存储器（1）包括存储单元阵列，字线（30,40,50,60），连接到字线的行解码器（9），位 线路（2,4,6,8），连接到位线的预充电电路（70,72,74,76,78,80），负载电路（22,23,24,25,26,27,28） ，29）和连接到所述位线的感测电路（12,14,16,18）。 存储器阵列包括浮置栅极MOSFET晶体管和以与字线和位线的相应子集相关联的组的开关MOSFET晶体管。 在每组中，浮动栅晶体管（32,34,42,44）和开关晶体管（35,45）的源极共同连接，浮栅晶体管的控制栅极和漏极分别连接到唯一的相关字 （30,40）相关的位线（2,4）对，并且每个开关晶体管的栅极连接到唯一的相关联的字线，并且其漏极连接到参考线（5）。 感测电流阈值被设置在由一个ON浮栅晶体管汲取的电流量与等于连接到单个位线的组中的浮栅晶体管的数量的多个OFF浮栅晶体管汲取的电流量之间， 减一。

公开(公告)号：US5357465A

公开(公告)日：1994-10-18

申请号：US26940

申请日：1993-03-05

申请人： Nagesh Challa

发明人： Nagesh Challa

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C13/00

CPC分类号： G11C16/26 ,  G11C16/0416 ,  G11C16/08

摘要： A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area wherein a tunneling of charge can take place between the drain and the floating gate by means of a system of applied voltages to the control gate and drain.

摘要翻译： 具有浮置栅极的单晶体管非易失性存储单元MOS晶体管和使用与漏极区域重叠的两层多晶硅和隧道电介质的控制栅极，其中可以通过装置在漏极和浮置栅极之间发生电荷的隧穿 一个施加电压的系统到控制栅极和漏极。

公开(公告)号：US5197027A

公开(公告)日：1993-03-23

申请号：US645507

申请日：1991-01-24

申请人： Nagesh Challa

发明人： Nagesh Challa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10

摘要： A single-transistor EEPROM device of the present invention comprises memory transistors in banks similar to NAND structures wherein the control gates of the memory transistors have negative voltages applied in various modes that allow reading, writing, and programming regardless of the V.sub.th of nonselected memory transistors in a bank. Programming and erasing results from various combinations of negative and positive voltages are used on the select gates together with positive voltages less than that alone which is necessary to induce Fowler-Nordheim tunneling are applied to the bit lines.

摘要翻译： 本发明的单晶体管EEPROM器件包括类似于NAND结构的存储器晶体管，其中存储晶体管的控制栅极具有以允许读取，写入和编程的各种模式施加的负电压，而与无选择的存储器晶体管的Vth无关。 在银行里。 在选择栅极上使用来自负电压和正电压的各种组合的编程和擦除结果，以及仅将诱导Fowler-Nordheim隧道施加到位线所需的正电压。

公开(公告)号：US20080035734A1

公开(公告)日：2008-02-14

申请号：US11891950

申请日：2007-08-14

申请人： Nagesh Challa ,  Venkata Gobburu

发明人： Nagesh Challa ,  Venkata Gobburu

IPC分类号： G06K7/10

CPC分类号： G06K7/10 ,  G06K7/1095 ,  G06K7/14 ,  G06K17/0022 ,  G06Q20/32 ,  G06Q20/322 ,  G06Q20/3274 ,  G06Q20/343 ,  G07F7/02 ,  G07G1/0045

摘要： Techniques are described for facilitating the reliable communication of information to bar code scanners from mobile digital devices, thereby enabling mobile digital devices to easily access the current commercial infrastructure. These techniques may be used to access many other goods and services in addition to conventional commercial services. The core enabling technology is the use of various elements commonly found on mobile digital devices to provide light that simulate a reflection of a scanning beam being moved across a static bar code image, and to confirm completion of the scan. The control system may interpret the light provided by the mobile digital device as merely a conventional identification type bar code, although the control system may be enhanced to identify and receive other types of information, including identity and credit information.

摘要翻译： 描述了便于从移动数字设备将信息可靠地传送到条形码扫描器的技术，从而使得移动数字设备能够容易地访问当前的商业基础设施。 除常规商业服务之外，这些技术可用于访问许多其他商品和服务。 核心使能技术是使用通常在移动数字设备上发现的各种元件来提供模拟扫描光束穿过静态条形码图像的反射并且确认扫描完成的光。 尽管控制系统可以被增强以识别和接收包括身份和信用信息在内的其他类型的信息，但是控制系统可以将由移动数字设备提供的光解释为传统的识别类型条形码。

公开(公告)号：US20070117552A1

公开(公告)日：2007-05-24

申请号：US11651127

申请日：2007-01-09

申请人： Venkata Gobburu ,  Nagesh Challa ,  Michel Gannage

发明人： Venkata Gobburu ,  Nagesh Challa ,  Michel Gannage

IPC分类号： H04Q7/38

CPC分类号： H04W4/10 ,  H04W76/45 ,  H04W84/08

摘要： Various communications clients such as, for example, Push to Talk over Cellular (“PoC”) client applications and PoC devices provided with client applications, provide extended services such as filler information for dead time intervals, and communication of PoC session content with non-PoC subscribers and with PoC subscribers who are offline. Through the use of one or more client applications to provide these extended services, the user experience is enriched and operators may monetize these extended services without need to modify the operating system or the network.

摘要翻译： 各种通信客户端，例如通过蜂窝通话（PoC）客户端应用和PoC设备提供的客户端应用提供诸如死时间间隔的填充信息等扩展服务，以及PoC会话内容与非客户端通信的通信， PoC订阅者和离线的PoC订阅者。 通过使用一个或多个客户端应用程序提供这些扩展服务，丰富了用户体验，运营商可以通过这些扩展服务获利，而无需修改操作系统或网络。

公开(公告)号：US20060202035A1

公开(公告)日：2006-09-14

申请号：US11369190

申请日：2006-03-06

申请人： Nagesh Challa ,  Venkata Gobburu

发明人： Nagesh Challa ,  Venkata Gobburu

IPC分类号： G06K7/10

CPC分类号： G06Q20/3274 ,  G06K7/1095 ,  G06K7/14 ,  G06K17/0022 ,  G06Q20/32 ,  G06Q20/322 ,  G06Q20/343 ,  G07F7/02 ,  G07G1/0045

摘要： A system, method, and apparatus for communicating information encoded in a bar code format between a mobile communications device and a bar code scanner. Transmission information data is encoded into a bar code format. A signal is generated from the bar code format to simulate a reflection of a scanning beam being moved across a static visual image of the bar code format; and the signal is transmitted as light pulses from the mobile communications device.