公开(公告)号：US20080082751A1

公开(公告)日：2008-04-03

申请号：US11864860

申请日：2007-09-28

申请人： Kenneth Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

发明人： Kenneth Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F13/1668 ,  G06F2212/205 ,  Y02D10/14

摘要： A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

摘要翻译： 公开了一种计算机系统，其包括包括多个迹线的印刷电路板（PCB），至少一个处理器，其安装到PCB以耦合到多个迹线中的一些，异质存储器通道，包括耦合到存储器的多个插座 PCB的通道总线，以及耦合在所述至少一个处理器和所述异构存储器通道之间的存储器控​​制器。 异质存储器通道包括耦合到PCB的存储器通道总线的多个插座。 多个插槽被配置为接收多个不同类型的存储器模块。 存储器控制器可以是可编程异构存储器控制器，以灵活地适应存储器通道总线来控制对异质存储器通道中的每种不同类型的存储器模块的访问。

公开(公告)号：US20150012721A1

公开(公告)日：2015-01-08

申请号：US14330930

申请日：2014-07-14

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

摘要翻译： 接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。 识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。 访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。 与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

公开(公告)号：US08745314B1

公开(公告)日：2014-06-03

申请号：US12490930

申请日：2009-06-24

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F13/1694 ,  G06F2212/211

摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

摘要翻译： 在本发明的一个实施例中，公开了一种存储装置。 存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。 存储器阵列是块读/写可访问和随机读取可访问的。 块读/写控制器耦合在存储器阵列和外部互连之间。 块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。 随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。 随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

公开(公告)号：US08677037B1

公开(公告)日：2014-03-18

申请号：US13163461

申请日：2011-06-17

申请人： Vijay Karamcheti ,  Ashwin Narasimha

发明人： Vijay Karamcheti ,  Ashwin Narasimha

IPC分类号： G06F13/12

CPC分类号： G06F13/1642 ,  G06F13/1657 ,  G06F13/1694

摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.

摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。

公开(公告)号：US20140075101A1

公开(公告)日：2014-03-13

申请号：US14016218

申请日：2013-09-02

申请人： Vijay Karamcheti ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kumar Ganapathy

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G11C5/04 ,  G11C29/76

摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

摘要翻译： 在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。 存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。 从存储器控制器从地址控制器接收存储器模块的存储器访问请求。 从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

公开(公告)号：US20140074880A1

公开(公告)日：2014-03-13

申请号：US14016223

申请日：2013-09-03

申请人： Vijay Karamcheti ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kumar Ganapathy

IPC分类号： G06F17/30

CPC分类号： G11C16/0408 ,  G06F7/78 ,  G06F12/0207 ,  G06F12/0246 ,  G06F12/0607 ,  G06F16/2455 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/06 ,  Y02D10/13

摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

摘要翻译： 在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。 存储器模块的多个存储器片中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。 从存储器控制器从地址控制器接收存储器模块的存储器访问请求。 从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

公开(公告)号：US08650343B1

公开(公告)日：2014-02-11

申请号：US13163571

申请日：2011-06-17

申请人： Ruban Kanapathippillai ,  Ashwin Narasimha ,  Kenneth A. Okin ,  Vijay Karamcheti

发明人： Ruban Kanapathippillai ,  Ashwin Narasimha ,  Kenneth A. Okin ,  Vijay Karamcheti

IPC分类号： G06F13/12 ,  G06F12/00

CPC分类号： G06F13/1694 ,  G06F13/1657 ,  Y02D10/14

摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

摘要翻译： 在本发明的一个实施例中，公开了一种可替换的存储装置。 可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。 第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。 第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。

公开(公告)号：US08429318B1

公开(公告)日：2013-04-23

申请号：US13163493

申请日：2011-06-17

申请人： Vijay Karamcheti ,  Ashwin Narasimha

发明人： Vijay Karamcheti ,  Ashwin Narasimha

IPC分类号： G06F13/12

CPC分类号： G06F13/1657

摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.

摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。

公开(公告)号：US20120254577A1

公开(公告)日：2012-10-04

申请号：US13493766

申请日：2012-06-11

申请人： Kenneth A. Okin ,  Vijay Karamcheti

发明人： Kenneth A. Okin ,  Vijay Karamcheti

IPC分类号： G06F12/02

CPC分类号： G06F12/02 ,  G06F11/1658 ,  G06F11/20 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7202 ,  G11C16/3418 ,  G11C16/3427

摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

公开(公告)号：US08266407B2

公开(公告)日：2012-09-11

申请号：US13053371

申请日：2011-03-22

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。