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公开(公告)号：US20100097856A1
公开(公告)日：2010-04-22
申请号：US12643610
申请日：2009-12-21
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译： 在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和 在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管 并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。 在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。
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公开(公告)号：US08804432B2
公开(公告)日：2014-08-12
申请号：US13454381
申请日：2012-04-24
摘要： Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.
摘要翻译： 公开了用于感测，存储器件和存储器系统的方法。 一种用于感测的方法包括将全位线架构的位线充电到预充电电压，选择字线以及对位线进行感测操作。 在对第一选定字线的存储单元进行感测操作完成之后，在选择第二字线的同时，在位线上保持预充电电压。
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公开(公告)号：US20130028022A1
公开(公告)日：2013-01-31
申请号：US13190911
申请日：2011-07-26
IPC分类号： G11C16/10
CPC分类号： G11C16/3436 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/3418 , G11C16/3422
摘要： Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb.
摘要翻译： 公开了用于确定程序窗口和存储器件的方法。 用于确定程序窗口的一种这样的方法测量由特定状态经历的程序干扰量，并且响应于程序干扰量确定程序窗口。
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公开(公告)号：US20120307564A1
公开(公告)日：2012-12-06
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译： 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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公开(公告)号：US08264882B2
公开(公告)日：2012-09-11
申请号：US13313379
申请日：2011-12-07
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
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26.发明授权Technique to reduce FG-FG interference in multi bit NAND flash memory in case of adjacent pages not fully programmed 有权在相邻页面未完全编程的情况下，减少多位NAND闪存中FG-FG干扰的技术公开(公告)号：US08194448B2
公开(公告)日：2012-06-05
申请号：US12647317
申请日：2009-12-24
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that have not been programmed.
摘要翻译： 提供了一种在编程NAND闪速存储器中减少浮置栅极 - 浮动栅极干扰的方法。 在对存储器单元的上部页进行编程之前，该方法包括检查邻近存储器单元的相邻页面是否被编程。 该方法可以编程尚未被编程的近的存储器单元的相邻页面。
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公开(公告)号：US20110194350A1
公开(公告)日：2011-08-11
申请号：US13090754
申请日：2011-04-20
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译： 在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。 通过偏置字线的读取操作产生位线电流。 作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。 在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。 这种背面图案效果指示用于随后的读取操作以调整操作的时间。
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公开(公告)号：US07944757B2
公开(公告)日：2011-05-17
申请号：US12718290
申请日：2010-03-05
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译： 本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。 该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的水平 并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。
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公开(公告)号：US07936606B2
公开(公告)日：2011-05-03
申请号：US12108067
申请日：2008-04-23
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of provided embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译： 在一个或多个所提供的实施例中，读取操作被补偿以用于背面图案效果。 通过偏置字线的读取操作产生位线电流。 作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。 在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。 这种背面图案效果指示用于随后的读取操作以调整操作的时间。
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公开(公告)号：US20110063920A1
公开(公告)日：2011-03-17
申请号：US12561692
申请日：2009-09-17
摘要： Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.
摘要翻译： 公开了用于感测，存储器件和存储器系统的方法。 一种用于感测的方法包括将全位线架构的位线充电到预充电电压，选择字线以及对位线进行感测操作。 在对第一选定字线的存储单元进行感测操作完成之后，在选择第二字线的同时，在位线上保持预充电电压。
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