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公开(公告)号：US20090290426A1
公开(公告)日：2009-11-26
申请号：US12123765
申请日：2008-05-20
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
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公开(公告)号：US08264882B2
公开(公告)日：2012-09-11
申请号：US13313379
申请日：2011-12-07
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
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公开(公告)号：US20120075932A1
公开(公告)日：2012-03-29
申请号：US13313379
申请日：2011-12-07
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
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公开(公告)号：US20100097856A1
公开(公告)日：2010-04-22
申请号：US12643610
申请日：2009-12-21
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译： 在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和 在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管 并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。 在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。
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公开(公告)号：US08085591B2
公开(公告)日：2011-12-27
申请号：US12123765
申请日：2008-05-20
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
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公开(公告)号：US08391061B2
公开(公告)日：2013-03-05
申请号：US12643610
申请日：2009-12-21
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译： 在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和 在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管 并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。 在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。
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公开(公告)号：US20080158986A1
公开(公告)日：2008-07-03
申请号：US11618652
申请日：2006-12-29
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell is programmed, a word-line voltage is coupled to the flash memory cell, and a state of the flash memory cell is sensed at intervals to generate data to indicate a state of the flash memory cell. In a method of operation, a latch in a cache memory of a NAND flash memory is switched off, and the latch is initialized while the latch is switched off. A read voltage is coupled to a gate of a selected flash memory cell in the NAND flash memory where the selected flash memory cell is coupled to a bit-line, and the bit-line is coupled to an input of the latch while a voltage on the bit-line is changing.
摘要翻译： 在一种操作方法中，闪存单元被编程，字线电压耦合到闪存单元，并且间隔地感测闪存单元的状态以产生数据以指示闪存单元的状态 。 在一种操作方法中，NAND闪存的高速缓冲存储器中的锁存器被关闭，并且在锁存器被关闭时初始化锁存器。 读取电压耦合到NAND闪速存储器中所选择的快闪存储器单元的栅极，其中所选闪存单元耦合到位线，并且位线耦合到锁存器的输入，同时电压开 位线正在改变。
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公开(公告)号：US08395939B2
公开(公告)日：2013-03-12
申请号：US13090754
申请日：2011-04-20
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译： 在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。 通过偏置字线的读取操作产生位线电流。 作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。 在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。 这种背面图案效果指示用于随后的读取操作以调整操作的时间。
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公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US08174897B2
公开(公告)日：2012-05-08
申请号：US13170420
申请日：2011-06-28
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件和存储器件的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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