公开(公告)号：US20090114983A1

公开(公告)日：2009-05-07

申请号：US12142802

申请日：2008-06-20

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ming-Jang Lin

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ming-Jang Lin

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766

Abstract: A power transistor capable of decreasing capacitance between a gate and a drain includes a backside mental layer, a substrate formed on the backside mental layer, a semiconductor layer formed on the substrate, and a frontside mental layer formed on the semiconductor layer. The semiconductor layer comprises a first trench structure comprising a gate oxide layer, a second trench structure comprising a p-well junction formed around a second trench, a p-body region formed outside the first trench structure and the second trench structure, a first n+ source region formed on the p-body region and beside a sidewall of the first trench structure, a second n+ source region formed on the p-body region and between another sidewall of the first trench structure and the second trench structure, and a dielectric layer formed on the first trench structure, the first n+ source region, and the second n+ source region.

Abstract translation: 能够降低栅极和漏极之间的电容的功率晶体管包括背面的精神层，形成在背面的精神层上的衬底，形成在衬底上的半导体层以及形成在半导体层上的前侧心理层。 半导体层包括包括栅极氧化物层的第一沟槽结构，包括围绕第二沟槽形成的p阱结的第二沟槽结构，形成在第一沟槽结构外部的p体区域和第二沟槽结构，第一n + 源区域形成在p体区域和第一沟槽结构的侧壁旁边，第二n +源极区域形成在p体区域上，在第一沟槽结构的另一个侧壁和第二沟槽结构之间，以及介电层 形成在第一沟槽结构上，第一n +源极区域和第二n +源极区域。

公开(公告)号：US20090061584A1

公开(公告)日：2009-03-05

申请号：US12030194

申请日：2008-02-12

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ming-Jang Lin ,  Hsin-Yen Chiu

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ming-Jang Lin ,  Hsin-Yen Chiu

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/66727 ,  H01L29/66734

Abstract: The present invention provides a semiconductor process for a trench power MOSFET. The semiconductor process includes providing a substrate, forming an EPI wafer on the surface, performing trench dry etching, performing HTP hard mask oxide deposition and channel self- align implant, performing boron (B) implant and completing the P-body region through a thermal process, performing arsenic (As) implant and completing the n+ source region through a thermal process, and depositing BPSG ILD, front side metal Al, and backside metal Ti/Ni/Ag.

Abstract translation: 本发明提供了一种用于沟槽功率MOSFET的半导体工艺。 半导体工艺包括提供衬底，在表面上形成EPI晶片，执行沟槽干蚀刻，执行HTP硬掩模氧化物沉积和通道自对准注入，执行硼（B）注入并通过热量完成P体区域 处理，通过热处理完成砷（As）注入和完成n +源区，并沉积BPSG ILD，前侧金属Al和背面金属Ti / Ni / Ag。

公开(公告)号：US08258555B2

公开(公告)日：2012-09-04

申请号：US13008908

申请日：2011-01-19

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L29/76

CPC classification number: H01L29/7813 ,  H01L28/60 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

Abstract: A semiconductor device includes a semiconductor substrate having a conductive type, a source metal layer, a gate metal layer, at least one transistor device, a heavily doped region having the conductive type, a capacitor dielectric layer, a conductive layer. The source metal layer and the gate metal layer are disposed on the semiconductor substrate. The transistor device is disposed in the semiconductor substrate under the source metal layer. The heavily doped region, the capacitor dielectric layer and the conductive layer constitute a capacitor structure, disposed under the gate metal layer, and the capacitor structure is electrically connected between a source and a drain of the transistor device.

Abstract translation: 半导体器件包括具有导电类型的半导体衬底，源极金属层，栅极金属层，至少一个晶体管器件，具有导电类型的重掺杂区域，电容器介电层，导电层。 源极金属层和栅极金属层设置在半导体衬底上。 晶体管器件设置在源极金属层下面的半导体衬底中。 重掺杂区域，电容器介电层和导电层构成电容器结构，设置在栅极金属层下方，并且电容器结构电连接在晶体管器件的源极和漏极之间。

公开(公告)号：US08217454B2

公开(公告)日：2012-07-10

申请号：US13025176

申请日：2011-02-11

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L29/66

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095

Abstract: A semiconductor device includes an epitaxial layer having a first conductive type, and at least one first semiconductor layer and a second semiconductor layer having a second conductive type. The first semiconductor layer is disposed in the epitaxial layer of a peripheral region, and has an arc portion, and a first strip portion and a second strip portion extended from two ends of the arc portion. The first strip portion points to an active device region, and the second strip portion is perpendicular to the first strip portion The second semiconductor layer is disposed in the epitaxial layer of the peripheral region between the active device region and the second strip portion, and the second semiconductor has a sidewall facing and parallel to the first semiconductor layer.

Abstract translation: 半导体器件包括具有第一导电类型的外延层和至少一个第一半导体层和具有第二导电类型的第二半导体层。 第一半导体层设置在周边区域的外延层中，具有弧形部分，以及从弧形部分的两端延伸的第一条带部分和第二条带部分。 第一条带部分指向有源器件区域，第二条带部分垂直于第一条带部分。第二半导体层设置在有源器件区域和第二条带部分之间的外围区域的外延层中，并且 第二半导体具有面向并平行于第一半导体层的侧壁。

公开(公告)号：US08168480B2

公开(公告)日：2012-05-01

申请号：US12563172

申请日：2009-09-21

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC: H01L21/332

CPC classification number: H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract translation: IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。

公开(公告)号：US08120100B2

公开(公告)日：2012-02-21

申请号：US12616770

申请日：2009-11-11

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

IPC: H01L27/108 ,  H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

Abstract: An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.

Abstract translation: 重叠沟槽栅极半导体器件包括半导体衬底，设置在半导体衬底上的多个浅沟槽，设置在浅沟槽中的第一导电层，分别设置在每个浅沟槽中的多个深沟槽，设置在第二导电层中的第二导电层 深沟槽，源极金属层和栅极金属层。 每个深沟槽在每个浅沟槽下延伸到半导体衬底中。 源极金属层电连接到第二导电层，并且栅极金属层电连接到第一导电层。

公开(公告)号：US20110254050A1

公开(公告)日：2011-10-20

申请号：US12760754

申请日：2010-04-15

Applicant: Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

Inventor： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

IPC: H01L29/74 ,  H01L21/332

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.

Abstract translation: 提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域 所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。 提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域 并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。 这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。

公开(公告)号：US20100301386A1

公开(公告)日：2010-12-02

申请号：US12563172

申请日：2009-09-21

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/77

CPC classification number: H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract translation: IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。

公开(公告)号：US20100285646A1

公开(公告)日：2010-11-11

申请号：US12507808

申请日：2009-07-23

Applicant: Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Guo-Liang Yang ,  Jen-Hao Yeh

Inventor： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Guo-Liang Yang ,  Jen-Hao Yeh

IPC: H01L21/336 ,  H01L21/768

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.

Abstract translation: 在衬底中形成更宽且更窄的沟槽。 沉积第一栅极材料层，但不完全填充较宽的沟槽。 通过各向同性或各向异性蚀刻来去除较宽沟槽中的第一栅极材料层和衬底原始表面之上。 第一掺杂剂层通过倾斜离子注入在原始表面和较宽沟槽的侧壁和底部形成在衬底的表面层中。 沉积第二栅极材料层以完全填充沟槽。 通过各向异性蚀刻去除原始表面上方的栅极材料层。 通过离子注入在原始表面的基板的表面层中形成第二掺杂剂层。 掺杂剂被驱入以在衬底中形成基底，并且围绕较宽沟槽的底部并且与基底相邻的底部轻掺杂层。

公开(公告)号：US20100258853A1

公开(公告)日：2010-10-14

申请号：US12477121

申请日：2009-06-02

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin

IPC: H01L29/78 ,  H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866

Abstract: A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost.

Abstract translation: 提供了沟槽半导体器件及其制造方法。 沟槽半导体器件包括沟槽MOS器件和沟槽ESD保护器件。 沟槽ESD保护器件电连接在沟槽MOS器件的栅电极和源电极之间，以提供ESD保护。 ESD保护器件的制造集成到沟槽MOS器件的工艺中，因此不需要额外的掩模来限定沟槽ESD保护器件的掺杂区域。 因此，沟槽半导体器件有利于其简化的制造工艺和低成本。