公开(公告)号：US20110254050A1

公开(公告)日：2011-10-20

申请号：US12760754

申请日：2010-04-15

申请人： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

发明人： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

摘要： An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.

摘要翻译： 提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域 所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。 提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域 并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。 这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。

公开(公告)号：US08564097B2

公开(公告)日：2013-10-22

申请号：US12760754

申请日：2010-04-15

申请人： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

发明人： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

IPC分类号： H01L27/082

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

摘要： An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.

摘要翻译： 提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域 所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。 提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域 并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。 这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。

公开(公告)号：US20120126328A1

公开(公告)日：2012-05-24

申请号：US13025176

申请日：2011-02-11

申请人： Wei-Chieh Lin

发明人： Wei-Chieh Lin

IPC分类号： H01L27/088

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095

摘要： A semiconductor device includes an epitaxial layer having a first conductive type, and at least one first semiconductor layer and a second semiconductor layer having a second conductive type. The first semiconductor layer is disposed in the epitaxial layer of a peripheral region, and has an arc portion, and a first strip portion and a second strip portion extended from two ends of the arc portion. The first strip portion points to an active device region, and the second strip portion is perpendicular to the first strip portion The second semiconductor layer is disposed in the epitaxial layer of the peripheral region between the active device region and the second strip portion, and the second semiconductor has a sidewall facing and parallel to the first semiconductor layer.

摘要翻译： 半导体器件包括具有第一导电类型的外延层和至少一个第一半导体层和具有第二导电类型的第二半导体层。 第一半导体层设置在周边区域的外延层中，具有弧形部分，以及从弧形部分的两端延伸的第一条带部分和第二条带部分。 第一条带部分指向有源器件区域，第二条带部分垂直于第一条带部分。第二半导体层设置在有源器件区域和第二条带部分之间的外围区域的外延层中，并且 第二半导体具有面向并平行于第一半导体层的侧壁。

公开(公告)号：US08178923B2

公开(公告)日：2012-05-15

申请号：US12840283

申请日：2010-07-20

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

IPC分类号： H01L23/48

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734

摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

摘要翻译： 提供了具有低栅极输入电阻的功率半导体器件及其制造方法。 功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。 金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。 因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

公开(公告)号：US20120056277A1

公开(公告)日：2012-03-08

申请号：US13013832

申请日：2011-01-26

申请人： Wei-Chieh Lin

发明人： Wei-Chieh Lin

IPC分类号： H01L29/78 ,  H01L23/495

CPC分类号： H01L23/49562 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823487 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.

摘要翻译： 本发明提供一种半导体器件，其包括具有第一导电类型的半导体衬底，至少一个高侧晶体管器件和至少一个低侧晶体管器件。 高侧晶体管器件包括具有第二导电类型的掺杂高侧基极区域，具有第一导电类型的掺杂高侧源极区域和具有第一导电类型的掺杂漏极区域。 掺杂的高侧基极区域设置在半导体衬底内，并且掺杂的高侧源极区域和掺杂漏极区域设置在掺杂的高侧基极区域内。 掺杂的高侧源极区域与半导体衬底电连接，半导体衬底被认为是低侧晶体管器件的漏极。

公开(公告)号：US08049273B2

公开(公告)日：2011-11-01

申请号：US12371618

申请日：2009-02-15

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

IPC分类号： H01L26/66

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916

摘要： A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

摘要翻译： 功率半导体器件包括背面金属层，形成在背面金属层上的衬底，形成在衬底上的半导体层和前侧金属层。 半导体层包括第一沟槽结构，其包括围绕具有多晶硅注入的第一沟槽形成的栅极氧化层，第二沟槽结构，包括围绕具有多晶硅注入的第二沟槽形成的栅极氧化层，形成的p基区 在所述第一沟槽结构和所述第二沟槽结构之间形成有多个n +源极区，形成在所述p基区上以及所述第一沟槽结构和所述第二沟槽结构之间，形成在所述第一沟槽结构上的介电层，所述第二沟槽结构 ，以及多个n +源极区域。 前半导体金属层形成在半导体层上并填充形成在p基区上的多个n +源极区之间的间隙。

公开(公告)号：US20100117142A1

公开(公告)日：2010-05-13

申请号：US12371618

申请日：2009-02-15

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

IPC分类号： H01L29/772

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916

摘要： A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

摘要翻译： 功率半导体器件包括背面金属层，形成在背面金属层上的衬底，形成在衬底上的半导体层和前侧金属层。 半导体层包括第一沟槽结构，其包括围绕具有多晶硅注入的第一沟槽形成的栅极氧化层，第二沟槽结构，包括围绕具有多晶硅注入的第二沟槽形成的栅极氧化层，形成的p基区 在所述第一沟槽结构和所述第二沟槽结构之间形成有多个n +源极区，形成在所述p基区上以及所述第一沟槽结构和所述第二沟槽结构之间，形成在所述第一沟槽结构上的介电层，所述第二沟槽结构 ，以及多个n +源极区域。 前半导体金属层形成在半导体层上并填充形成在p基区上的多个n +源极区之间的间隙。

公开(公告)号：US07682903B1

公开(公告)日：2010-03-23

申请号：US12334492

申请日：2008-12-14

申请人： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

发明人： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66734

摘要： A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.

摘要翻译： 一种形成功率器件的方法包括提供衬底，至少具有沟槽并设置在衬底上的半导体层，覆盖半导体层的栅极绝缘层和设置在沟槽中的导电材料，执行离子注入工艺 从体层进行倾斜的离子注入工艺，从重掺杂区域进行倾斜的离子注入工艺，整体形成第一介电层，进行化学机械抛光工艺，直到布置在重掺杂区域之下的体层露出，形成源区 并且形成直接覆盖设置在沟槽的相对侧上的源极区域的源极迹线。

公开(公告)号：US08441067B2

公开(公告)日：2013-05-14

申请号：US13070479

申请日：2011-03-24

申请人： Wei-Chieh Lin

发明人： Wei-Chieh Lin

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.

摘要翻译： 具有低寄生晶体管的功率器件包括凹陷晶体管和位于凹陷晶体管的源极区一侧的重掺杂区域。 重掺杂区域的导电类型与源极区域的导电类型不同。 此外，接触插塞接触重掺杂区域并电连接重掺杂区域。 源极线覆盖并接触源极区域和接触插塞以使源极区域和重掺杂区域具有相同的电势。

公开(公告)号：US08198684B2

公开(公告)日：2012-06-12

申请号：US12614434

申请日：2009-11-08

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0255 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

摘要翻译： 具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。 半导体衬底的上表面具有第一沟槽和第二沟槽。 沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。 沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。