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公开(公告)号：US11984919B2
公开(公告)日：2024-05-14
申请号：US17959079
申请日：2022-10-03
Applicant: XILINX, INC.
Inventor： Hongzhi Zhao , Christophe Erdmann , Hemang M. Parekh , Xing Zhao , Xiaohan Chen
Abstract: Embodiments herein describe a PIM correction circuit. In a base station, TX and RX RF changes, band pass filters, duplexers, and diplexers can have severe memory effects due to their sharp transition bandwidth from pass band to stop band. PIM interference, generated by the TX signals and reflected onto the RX RF chain will include these memory effects. These memory effects make PIM cancellation complex, requiring complicated computations and circuits. However, the embodiments herein use a PIM correction circuit that separates the memory effects of the TX and RX paths from the memory effects of PIM, thereby reducing PIM cancellation complexity and hardware implementation cost.
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公开(公告)号：US11923856B2
公开(公告)日：2024-03-05
申请号：US17713901
申请日：2022-04-05
Applicant: XILINX, INC.
Inventor： Bob W. Verbruggen , Christophe Erdmann
CPC classification number: H03K5/14 , H03K5/135 , H03K5/15066 , H03K19/0948 , H03M1/82 , H03K2005/00026
Abstract: Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.
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公开(公告)号：US10581450B1
公开(公告)日：2020-03-03
申请号：US16249230
申请日：2019-01-16
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , Bob W. Verbruggen , Christophe Erdmann , Roberto Pelliconi
Abstract: Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node VDD and a switch cell circuit to provide a predetermined resistance in response to the VDD and current IS of the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply VDD.
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公开(公告)号：US10419011B1
公开(公告)日：2019-09-17
申请号：US16108003
申请日：2018-08-21
Applicant: Xilinx, Inc.
Inventor： Roberto Pelliconi , Christophe Erdmann , Derek Chang
Abstract: An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.
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公开(公告)号：US10218372B1
公开(公告)日：2019-02-26
申请号：US15939257
申请日：2018-03-28
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , Christophe Erdmann , John E. McGrath , Bruno Miguel Vaz
IPC: H03M1/10
Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.
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Patent Agency Ranking
公开(公告)号：US09935597B2
公开(公告)日：2018-04-03
申请号：US15167197
申请日：2016-05-27
Applicant: Xilinx, Inc.
Inventor： Christophe Erdmann , Diarmuid Collins , Edward Cullen , Ionut C. Cical
CPC classification number: H03F3/45179 , H03F1/301 , H03F1/56 , H03F3/45183 , H03F2200/459 , H03F2203/45288
Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.
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公开(公告)号：US09680492B1
公开(公告)日：2017-06-13
申请号：US15246369
申请日：2016-08-24
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , Christophe Erdmann
CPC classification number: H03M1/0863 , H03M1/462 , H03M1/468
Abstract: An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs in a default state such that the sampled analog voltage is unchanged. Otherwise, the state machine is configured to switch the first pair of the plurality of capacitor pairs to change the sampled analog voltage.
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公开(公告)号：US11211921B2
公开(公告)日：2021-12-28
申请号：US16812130
申请日：2020-03-06
Applicant: Xilinx, Inc.
Inventor： Roswald Francis , Christophe Erdmann
IPC: H03K17/12 , H03K3/356 , H03K3/021 , H03K17/16 , H03K19/003 , H03K17/687
Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.
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公开(公告)号：US10998864B1
公开(公告)日：2021-05-04
申请号：US16583789
申请日：2019-09-26
Applicant: Xilinx, Inc.
Inventor： Roswald Francis , Christophe Erdmann
Abstract: An apparatus for generating an output current including a first distortion current based on a first transconductance and a second distortion current based on a second transconductance is disclosed. The first distortion current may be generated by an amplifier and the second distortion current may be generated by a distortion compensator. The second transconductance may be less than the first transconductance. In some implementations, the second distortion current may reduce the first distortion current output by the apparatus.
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公开(公告)号：US10862500B1
公开(公告)日：2020-12-08
申请号：US16683731
申请日：2019-11-14
Applicant: Xilinx, Inc.
Inventor： Roberto Pelliconi , Bob Verbruggen , Brendan Farley , Christophe Erdmann
Abstract: Apparatus and associated methods relate to maintaining a total current of a switch cell in a digital-to-analog converter at a controllable operating point by adjusting shunt current control signals applied to programmable shunt current sources in opposite polarity with respect to a tail current control signal applied to a programmable tail current source. In an illustrative example, the total current may flow through differential legs of a switch cell. The programmable shunt current sources may, for example, be configured to compensate for adjustments to the programmable tail current source. In an illustrative example, tail current and shunt currents may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current sources to compensate adjustments to the tail current source may, for example, permit controlled common mode voltage or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages.
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