公开(公告)号：US10770430B1

公开(公告)日：2020-09-08

申请号：US16361617

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

公开(公告)号：US10720377B2

公开(公告)日：2020-07-21

申请号：US16186178

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ho Hyung Lee ,  Hui-Wen Lin ,  Henley Liu ,  Suresh Ramalingam

IPC: H01L29/40 ,  H01L23/40 ,  H01L23/48 ,  H01L23/00 ,  H01L23/427

Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.

公开(公告)号：US10692837B1

公开(公告)日：2020-06-23

申请号：US16041530

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Nui Chong

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

公开(公告)号：US10431565B1

公开(公告)日：2019-10-01

申请号：US15907034

申请日：2018-02-27

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang

IPC: H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L23/00

Abstract: A stacked wafer assembly and method for fabricating the same are described herein. In one example, a stacked wafer assembly includes a first wafer bonded to a second wafer. The first wafer includes a plurality of fully functional dies and a first partial die formed thereon. The second wafer includes a plurality of fully functional dies and a first partial die formed thereon. Bond pads formed over an inductor of the first partial die of the first wafer are bonded to bond pads formed on the first partial die of the second wafer to establish electrical connection therebetween.

公开(公告)号：US10319606B1

公开(公告)日：2019-06-11

申请号：US15813008

申请日：2017-11-14

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H01L23/14

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.