公开(公告)号：USD538228S1

公开(公告)日：2007-03-13

申请号：US29259883

申请日：2006-05-18

Applicant: Yao-Ting Wang ,  Mu-Tsun Tseng

Designer： Yao-Ting Wang ,  Mu-Tsun Tseng

公开(公告)号：US20060242618A1

公开(公告)日：2006-10-26

申请号：US11354398

申请日：2006-02-14

Applicant: Yao-Ting Wang ,  Chi-Ming Tsai ,  Fang-Cheng Chang

Inventor： Yao-Ting Wang ,  Chi-Ming Tsai ,  Fang-Cheng Chang

IPC: G06F17/50

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/705 ,  G06F17/5081

Abstract: Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography checking, and model-based DRC, where operations of one or more techniques are run in parallel. The systems and methods provided also include the integration of lithographic geometry operations into GPUs to obtain improved performance. Examples of this integration include a Design Rule Checker (DRC), parasitic extraction, and placement and route for example.

Abstract translation: 提供了用于编程和运行GPU上光刻仿真的仿真引擎的系统和方法。 光刻模拟的这种集成包括在一个或多个GPU上托管各种光刻技术中的任何一种，包括例如分辨率增强技术，光学邻近校正，光学规则检查或光刻检查以及基于模型的DRC，其中操作 一个或多个技术并行运行。 所提供的系统和方法还包括将平版印刷几何操作集成到GPU中以获得改进的性能。 这种集成的示例包括设计规则检查器（DRC），寄生提取，以及放置和路由。

公开(公告)号：US06795168B2

公开(公告)日：2004-09-21

申请号：US10117838

申请日：2002-04-08

Applicant: Yao-Ting Wang ,  Christophe Pierrat ,  Fang-Cheng Chang

Inventor： Yao-Ting Wang ,  Christophe Pierrat ,  Fang-Cheng Chang

IPC: G03B2754

CPC classification number: G03F7/70208 ,  G03F7/70283

Abstract: One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.

Abstract translation: 本发明的一个实施例提供一种在集成电路制造过程中有助于使晶片通过至少两个掩模的系统。 该系统包括辐射源和两个或更多个照明器。 这些照明器中的每一个接收来自辐射源的辐射，并且使用辐射来照射标线架座。 然后通过每个光罩保持器的辐射在光合成器中通过成像光学器件，成像光学器件将组合的辐射投影到半导体晶片上。

公开(公告)号：US06757645B2

公开(公告)日：2004-06-29

申请号：US09130996

申请日：1998-08-07

Applicant: Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati ,  Linard N. Karklin

Inventor： Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati ,  Linard N. Karklin

IPC: G06F1750

CPC classification number: G06T7/0004 ,  G03F1/26 ,  G03F1/36 ,  G03F1/84 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5068 ,  G06T2207/30148

Abstract: A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.

公开(公告)号：US06584609B1

公开(公告)日：2003-06-24

申请号：US09514551

申请日：2000-02-28

Applicant: Christophe Pierrat ,  You-Ping Zhang ,  Fang-Cheng Chang ,  Hoyong Park ,  Yao-Ting Wang

Inventor： Christophe Pierrat ,  You-Ping Zhang ,  Fang-Cheng Chang ,  Hoyong Park ,  Yao-Ting Wang

IPC: G06F1750

CPC classification number: G03F1/70 ,  G03F1/36 ,  G06F17/5068

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract translation: 公开了一种半导体布局测试和校正系统。 该系统结合基于规则的光学邻近校正和基于模型的光学邻近校正，以便测试和校正半导体布局。 在第一实施例中，半导体布局首先由基于规则的光学邻近校正系统处理，然后由基于模型的光学邻近校正系统进行处理。 在另一个实施例中，系统首先使用基于规则的光学邻近校正系统处理半导体布局，然后使用基于模型的光学邻近校正系统来选择性地处理困难的特征。 在另一个实施例中，系统使用基于规则的光学邻近校正系统或基于模型的光学邻近校正系统选择性地处理半导体布局的各种特征。

公开(公告)号：US06566023B2

公开(公告)日：2003-05-20

申请号：US10154858

申请日：2002-05-24

Applicant: Yao-Ting Wang ,  Yagyensh C. Pati

Inventor： Yao-Ting Wang ,  Yagyensh C. Pati

IPC: G03F900

CPC classification number: G03F7/70283 ,  G03F1/26 ,  G03F1/30 ,  G03F1/34 ,  G03F1/36 ,  G03F1/70 ,  G03F7/2022 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5068

Abstract: A two mask process for small dimension features on an integrated circuit improves manufacturability and design tolerance. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.

Abstract translation: 集成电路上的小尺寸特征的两个掩模过程提高了可制造性和设计容差。 第一掩模是不透明场相移掩模，第二掩模是单相结构掩模。 使用不透明场上的相移重叠区域将相移窗与不透明场对准。 相移掩模主要限定需要相移的区域。 单相结构掩模主要限定不需要相移的区域。 单相结构掩模还防止相移区域的擦除，并且防止产生否则将由相移掩模产生的不期望的伪影区域。

公开(公告)号：US06523162B1

公开(公告)日：2003-02-18

申请号：US09632080

申请日：2000-08-02

Applicant: Deepak Agrawal ,  Fang-Cheng Chang ,  Hyungjip Kim ,  Yao-Ting Wang ,  Myunghoon Yoon

Inventor： Deepak Agrawal ,  Fang-Cheng Chang ,  Hyungjip Kim ,  Yao-Ting Wang ,  Myunghoon Yoon

IPC: G06F1750

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table. The bias table can include both rule-based and model-based actions, and can also include single-edge shapes for completeness. The scanning of the IC layout can be performed in order of increasing or decreasing complexity, or can be specified by the user. The appropriate layout processing actions are applied to matching portions of the IC layout to form the corrected photomask layout. This process can be sequential or batch mode. Shape and action conflicts can be resolved by marking identified/modified elements or by designing rules for orderly resolution of any inconsistencies or overlaps.

Abstract translation: 布局处理可以应用于使用基于形状的系统的集成电路（IC）布局。 形状可以由指定配置中的一组关联边界来定义。 定义了一个形状的目录，并且布局处理动作与各种形状相关联。 每个布局处理动作都对其关联的形状应用指定的布局修改。 基于形状的规则系统有利地实现了布局修改的有效配置和精确应用。 形状/动作可以作为默认值提供，可以从远程源检索，也可以由用户定义。 布局处理动作可以在偏置表中进行编译。 偏置表可以包括基于规则的和基于模型的动作，并且还可以包括单边形状以获得完整性。 IC布局的扫描可以按照增加或减少的复杂性的顺序执行，或者可以由用户指定。 将适当的布局处理动作应用于IC布局的匹配部分以形成校正的光掩模布局。 此过程可以是顺序或批处理模式。 形状和行动冲突可以通过标记识别/修改的元素或通过设计规则来解决，以有序地解决任何不一致或重叠。

公开(公告)号：US06228539B1

公开(公告)日：2001-05-08

申请号：US09229455

申请日：1999-01-12

Applicant: Yao-Ting Wang ,  Yagyensh Pati

Inventor： Yao-Ting Wang ,  Yagyensh Pati

IPC: G03F900

CPC classification number: G03F7/70283 ,  G03F1/26 ,  G03F1/30 ,  G03F1/34 ,  G03F1/36 ,  G03F1/70 ,  G03F7/2022 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5068

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract translation: 一种用于产生相移掩模和用于收缩集成电路设计的结构掩模的方法和装置。 本发明的一个实施例包括使用两个掩模过程。 第一掩模是相移掩模，第二掩模是单相结构掩模。 相移掩模主要限定需要相移的区域。 单相结构掩模主要限定不需要相移的区域。 单相结构掩模还防止相移区域的擦除，并且防止产生否则将由相移掩模产生的不期望的伪影区域。 两个掩模都是从一个更大的最小尺寸工艺技术中使用的一组掩模派生出来的。

公开(公告)号：US08262417B1

公开(公告)日：2012-09-11

申请号：US13210472

申请日：2011-08-16

Applicant: Yao-Ting Wang ,  Yu-Hung Su

Inventor： Yao-Ting Wang ,  Yu-Hung Su

IPC: H01R24/00

CPC classification number: H01R13/6581 ,  H01R12/724

Abstract: An electrical connector includes an insulating housing, a dielectric body, a plurality of conductive terminals and a metallic piece. The insulating housing has a top wall, a bottom wall, a rear wall and two opposite side walls which together define an accommodating space thereamong. Two sides of a bottom of the top wall define two receiving grooves. The dielectric body has a base portion fastened in the rear wall, and a tongue portion penetrating forward through the rear wall to be inserted in the accommodating space. The conductive terminals are disposed in the dielectric body. The metallic piece has a base plate molded in the top wall. Two sides of the base plate respectively define an opening corresponding to the receiving groove. A front side of the opening is slantwise bent upward to form a clipping portion located in the receiving groove.

Abstract translation: 电连接器包括绝缘壳体，电介质体，多个导电端子和金属片。 绝缘壳体具有顶壁，底壁，后壁和两个相对的侧壁，它们共同限定了容纳空间。 顶壁的底部的两侧限定两个接收槽。 电介质本体具有紧固在后壁中的基部，以及舌部，其穿过后壁向前穿过以插入容纳空间。 导电端子设置在电介质体内。 金属片具有模制在顶壁中的基板。 基板的两侧分别限定与接收槽对应的开口。 开口的前侧向上倾斜弯曲以形成位于接收槽中的夹持部。

公开(公告)号：USD661658S1

公开(公告)日：2012-06-12

申请号：US29406710

申请日：2011-11-17

Applicant: Yao-Ting Wang ,  Yu-Hung Su

Designer： Yao-Ting Wang ,  Yu-Hung Su