公开(公告)号：US07495479B1

公开(公告)日：2009-02-24

申请号：US11854560

申请日：2007-09-13

Applicant: Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

Inventor： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC: H03K17/00

CPC classification number: G11C27/024 ,  G11C27/026

Abstract: Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

Abstract translation: 公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

公开(公告)号：US07228468B2

公开(公告)日：2007-06-05

申请号：US11001345

申请日：2004-11-30

Applicant: Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

Inventor： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

IPC: G11C29/00

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/44 ,  G11C29/72 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

Abstract translation: 本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。 它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。 基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。 它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重新配置电路。 本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。 它还增加了修复率，并减少了所需的面积开销。

公开(公告)号：US20060136793A1

公开(公告)日：2006-06-22

申请号：US11116402

申请日：2005-04-28

Applicant: Yaw-Feng Wang ,  Wen-Tsan Hsieh ,  Yi-Fang Chiu ,  Sheng-Yu Hsu ,  Yeong-Jar Chang

Inventor： Yaw-Feng Wang ,  Wen-Tsan Hsieh ,  Yi-Fang Chiu ,  Sheng-Yu Hsu ,  Yeong-Jar Chang

IPC: G11C29/00 ,  G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating mode and a variation of the data and/or address status of the memory device.

公开(公告)号：US20050174273A1

公开(公告)日：2005-08-11

申请号：US10894054

申请日：2004-07-20

Applicant: Pei-Wen Luo ,  Yeong-Jar Chang ,  Jung-Chi Ho ,  Wen-Ching Wu

Inventor： Pei-Wen Luo ,  Yeong-Jar Chang ,  Jung-Chi Ho ,  Wen-Ching Wu

IPC: G01R31/28 ,  H03M1/10 ,  H03M3/00

CPC classification number: H03M3/378 ,  H03M3/458

Abstract: IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.

Abstract translation: IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。 此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

公开(公告)号：US20050057312A1

公开(公告)日：2005-03-17

申请号：US10749560

申请日：2004-01-02

Applicant: Yeong-Jar Chang ,  Shen-Tien Lin ,  Wen-Ching Wu ,  Kun-Lun Luo

Inventor： Yeong-Jar Chang ,  Shen-Tien Lin ,  Wen-Ching Wu ,  Kun-Lun Luo

IPC: G01R29/26 ,  H03L7/06 ,  H03L7/00

CPC classification number: G01R29/26 ,  H03L7/06

Abstract: A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.

公开(公告)号：US08404501B2

公开(公告)日：2013-03-26

申请号：US12961512

申请日：2010-12-07

Applicant: Po-Yao Huang ,  Chia-Yu Jin ,  Yeong-Jar Chang

Inventor： Po-Yao Huang ,  Chia-Yu Jin ,  Yeong-Jar Chang

IPC: H01L21/00 ,  H01L27/15 ,  H01L31/12 ,  H01L33/00

CPC classification number: G02B6/4292 ,  G02B6/4214 ,  G02B6/4249 ,  G02B6/4251 ,  G02B6/4253 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/428 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package structure includes a package substrate, at least a chip, solder balls, a light emitting/receiving device, a optical intermediary device and an optical transmission device. The package substrate has a first surface, a second surface, a circuit and solder ball pads, wherein each solder ball pad is electrically connected to the circuit. The chip is disposed on the first surface and electrically connected to the circuit. The solder balls are respectively disposed on the solder ball pads. The light emitting/receiving device is disposed on the package substrate and electrically connected to the circuit. The optical intermediary device is disposed above the light emitting/receiving device. The optical transmission device is inserted in the optical intermediary device, wherein a light emitting by the light emitting/receiving device is emitted to the optical transmission device via the optical intermediary device so that an optical signal is transmitted through the optical transmission device.

Abstract translation: 半导体封装结构包括封装衬底，至少芯片，焊球，发光/接收器件，光中介器件和光传输器件。 封装衬底具有第一表面，第二表面，电路和焊球垫，其中每个焊球焊盘电连接到电路。 芯片设置在第一表面上并电连接到电路。 焊球分别设置在焊球垫上。 发光/接收装置设置在封装基板上并与电路电连接。 光中继装置设置在发光/接收装置的上方。 光传输装置被插入到光中继装置中，其中由发光/接收装置发射的光经由光中介装置发射到光传输装置，使得光信号通过光传输装置传输。

公开(公告)号：US07904874B2

公开(公告)日：2011-03-08

申请号：US12010136

申请日：2008-01-22

Applicant: Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

Inventor： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

IPC: G06F17/50

CPC classification number: G06F1/10

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract translation: 我们提出了用于峰值电流降低的反相方案。 基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段 时钟源。 因此，我们的方法可以有效地降低时钟树的峰值电流。 该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。

公开(公告)号：US20090096439A1

公开(公告)日：2009-04-16

申请号：US11870113

申请日：2007-10-10

Applicant: Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

Inventor： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC: G01R29/26 ,  G01R23/12

CPC classification number: G01R29/26 ,  G01R31/31709

Abstract: A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.

Abstract translation: 公开了抖动测量电路和校准抖动测量电路的方法。 抖动测量电路包括同步双相检测器和判定电路。 在测试模式中，获得由被测电路输出的时钟信号的抖动的概率分布函数（PDF）。 在校准模式中，由被测电路中的自由振荡器外部产生或产生的随机时钟用于校准同步双相检测器。 决定电路对由同步双相检测器检测的相位关系进行逻辑运算，数据锁存和计数，以获得相对于时钟信号的抖动的计数值和PDF。

公开(公告)号：US07475367B2

公开(公告)日：2009-01-06

申请号：US11116402

申请日：2005-04-28

Applicant: Yaw-Feng Wang ,  Wen-Tsan Hsieh ,  Yi-Fang Chiu ,  Sheng-Yu Hsu ,  Yeong-Jar Chang

Inventor： Yaw-Feng Wang ,  Wen-Tsan Hsieh ,  Yi-Fang Chiu ,  Sheng-Yu Hsu ,  Yeong-Jar Chang

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating mode and a variation of the data and/or address status of the memory device.

Abstract translation: 提供了一种用于存储器件的功耗模型。 根据每个特征向量，构建相应的功率查找表。 每个特征向量包括操作模式和存储器件的数据和/或地址状态的变化。

公开(公告)号：US20080186072A1

公开(公告)日：2008-08-07

申请号：US11754783

申请日：2007-05-29

Applicant: Chia-Wei Chang ,  Yeong-Jar Chang

Inventor： Chia-Wei Chang ,  Yeong-Jar Chang

IPC: H03H11/26

CPC classification number: H03H11/265

Abstract: A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.

Abstract translation: 可控延迟线包括抗抖动单元，依赖电流源，第一电流镜，第二电流镜，调节电容器，补偿电容器和输出缓冲器单元。 抗抖动单元接收第一偏置电压并且基于第一偏置电压产生第二偏置电压。 当在可控延迟线中使用的电压源具有变化时，第二偏置电压随之变化。 调节电容器用于减小电压源与第一电流源的节点电压之间的电压差的变化。 补偿电容器用于减小输出缓冲器单元的输入信号对节点电压的转变的影响，以便降低输出缓冲器单元的输出信号的抖动量。