公开(公告)号：US07459950B2

公开(公告)日：2008-12-02

申请号：US11553014

申请日：2006-10-26

申请人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

发明人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

IPC分类号： H03K3/017

CPC分类号： H03K3/017 ,  G01R31/31727 ,  G06F1/10 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156

摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.

摘要翻译： 在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。 输出驱动器输出脉宽调整信号。 脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。 第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。 脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。 可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

公开(公告)号：US20080116938A1

公开(公告)日：2008-05-22

申请号：US11560440

申请日：2006-11-16

申请人： Hung C. Ngo ,  Peter Juergen Klim ,  Jente B. Kuang ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

发明人： Hung C. Ngo ,  Peter Juergen Klim ,  Jente B. Kuang ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/0013

摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The dynamic node is coupled to an output with an inverting logic circuit. A hybrid keeper circuit, coupled to the dynamic node, uses a parallel NFET and a first PFET to produce the same current as a larger PFET when operated with a high voltage power supply. The common node of the combination is coupled to the dynamic node by second PFET larger than the first PFET in one embodiment. At high voltage, the hybrid keeper provides a strong keeper current when potential noise is highest. The hybrid keeper current is automatically reduced at low voltage allowing performance to be maintained while keeping the effective noise immunity of the high voltage operation.

摘要翻译： 动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点 逻辑输入的布尔组合。 动态节点与反相逻辑电路耦合到输出端。 耦合到动态节点的混合保持器电路使用并联NFET和第一PFET在用高压电源操作时产生与较大PFET相同的电流。 在一个实施例中，组合的公共节点通过大于第一PFET的第二PFET耦合到动态节点。 在高电压下，当潜在噪声最高时，混合式保持器提供强的保持电流。 混合保持器电流在低电压下自动降低，从而保持性能得以保持，同时保持高电压工作的有效抗噪声能力。

公开(公告)号：US07061265B2

公开(公告)日：2006-06-13

申请号：US10916980

申请日：2004-08-12

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

IPC分类号： H03K19/03

CPC分类号： H03K17/167 ,  H03K19/0016

摘要： Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials of the power supply from circuitry with large high leakage devices. Driver circuits comprise a low leakage logic path for holding logic states of the output. A high leakage logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each high leakage path that enhances the current drive of a logic state on the output are leakage stress relieved by allowing their drive inputs to collapse after the output logic state has been asserted. The high leakage logic paths employ multiple stages with collapsing logic states that are generated in response to asserted logic states on the output and logic states of the low leakage logic path thus reducing the device sizes needed to control leakage.

公开(公告)号：US07046063B2

公开(公告)日：2006-05-16

申请号：US10821047

申请日：2004-04-08

申请人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： H03K3/356

CPC分类号： H03K3/356008 ,  H03K19/0016 ,  H03K19/018521

摘要： CMOS circuitry is partitioned into first and second logic circuit domains. The first logic circuit domain may be optionally a cuttable domains (C_Domains) where circuitry has power supply gating to reduce leakage power and non-cuttable domains (NC_Domains) where circuitry does not have power supply gating. Each output that couples signals from one logic circuit domain to another logic circuit is interfaced with a C_driver and a S_keeper which automatically assure that the output state is held when circuitry is power-gated put to reduce leakage power. The S_keeper and C_driver have low leakage circuits that maintain signal states and are not used for high speed operation.

摘要翻译： CMOS电路分为第一和第二逻辑电路域。 第一逻辑电路域可以是可选择的可切割域（C_Domain），其中电路具有电源选通以减少泄漏功率和电路不具有电源门控的不可切割域（NC_Domain）。 将信号从一个逻辑电路域耦合到另一个逻辑电路的每个输出端与C_driver和S_keeper接口，该电路可以自动确保在电路门控电源降低漏电功率时保持输出状态。 S_keeper和C_driver具有低泄漏电路，保持信号状态，不用于高速运行。

公开(公告)号：US20080141046A1

公开(公告)日：2008-06-12

申请号：US11567395

申请日：2006-12-06

申请人： Lei Chen ,  Jente B. Kuang ,  Brian R. Mestan ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Lei Chen ,  Jente B. Kuang ,  Brian R. Mestan ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F9/30014 ,  G06F9/30105 ,  G06F9/30112

摘要： The present invention relates to a methodology for controlling the power consumption in a computing device based upon extended register file extension values, the method further comprising the steps of identifying an upper bit data register value and a lower bit data register value for a data register value, and inputting the upper bit data register value to a detect logic component, wherein the upper bit data register value is used to generate a data register extension value. The method further comprises the steps of utilizing the data register extension value as a power control signal serving to activate or deactivate a power supply signal to a segment of a data path, and updating the data register extension value in a subsequent data register write computational function.

摘要翻译： 本发明涉及一种用于基于扩展寄存器文件扩展值来控制计算设备中的功耗的方法，所述方法还包括以下步骤：识别数据寄存器值的高位数据寄存器值和低位数据寄存器值 ，并将高位数据寄存器值输入到检测逻辑分量，其中高位数据寄存器值用于产生数据寄存器扩展值。 该方法还包括以下步骤：利用数据寄存器扩展值作为用于激活或去激活到数据路径的段的电源信号的功率控制信号，以及在随后的数据寄存器写入计算功能中更新数据寄存器扩展值 。

公开(公告)号：US20080115019A1

公开(公告)日：2008-05-15

申请号：US11559436

申请日：2006-11-14

申请人： Hung C. Ngo ,  Gary D. Carpenter ,  Alan J. Drake ,  Jente B. Kuang

发明人： Hung C. Ngo ,  Gary D. Carpenter ,  Alan J. Drake ,  Jente B. Kuang

IPC分类号： G01R31/28

CPC分类号： G01R31/31727 ,  G01R31/31725 ,  G01R31/31726

摘要： An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.

摘要翻译： 具有可选路径环形振荡器电路的在线定时监视器在实际电路环境中提供延迟和性能测量。 测试模式信号被施加到数字电路以取消选择施加到数字电路内的功能逻辑块的给定功能输入信号，并且当选择测试模式操作时，将其与从功能逻辑块的输出耦合的反馈替换 。 选择从选择输入到输出的信号路径，使得信号路径振荡，并且测量输出信号的特征频率或相位以确定延迟。 将功能逻辑块的其他输入设置为预定的一组逻辑值。 可以在数字输入之前的寄存器处进行选择，或者在功能逻辑块的逻辑的第一级中进行选择。

公开(公告)号：US07323908B2

公开(公告)日：2008-01-29

申请号：US11260571

申请日：2005-10-27

申请人： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

发明人： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K3/03

CPC分类号： G01R31/31725

摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

摘要翻译： 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

公开(公告)号：US07298176B2

公开(公告)日：2007-11-20

申请号：US11204401

申请日：2005-08-16

申请人： Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

发明人： Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

IPC分类号： H03K19/20

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

摘要翻译： 动态逻辑门具有非对称双栅极PFET器件，用于在时钟的预充电阶段期间对动态节点进行充电。 逻辑树在时钟的评估阶段评估动态节点。 非对称双栅极PFET器件的前栅极耦合到时钟信号，而后栅极耦合到电源的地电位。 当时钟为逻辑0时，前门和后门都被偏置为ON，动态节点以最大电流充电。 在时钟关断前门的评估阶段，时钟信号转变为逻辑1。 背栅保持接通，并且非对称双栅极PFET器件作为具有足以抵抗动态节点上的泄漏的电流水平的保持器器件工作。

公开(公告)号：US07288975B2

公开(公告)日：2007-10-30

申请号：US11260563

申请日：2005-10-27

申请人： Hung C. Ngo ,  Gary D. Carpenter ,  Fadi H. Gebara ,  Jente B. Kuang

发明人： Hung C. Ngo ,  Gary D. Carpenter ,  Fadi H. Gebara ,  Jente B. Kuang

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  G06F1/04

摘要： A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

公开(公告)号：US07266707B2

公开(公告)日：2007-09-04

申请号：US10942419

申请日：2004-09-16

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

IPC分类号： G06F1/00

CPC分类号： G06F1/3228

摘要： A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

摘要翻译： 低功耗流水线电路架构具有电源分配管线级。 第一个流水线阶段是非功率门控，用于在接收到有效的数据信号后处理输入数据的快速响应。 电源门控第二管道级具有两个电源门控模式。 通常，电源门控第二管线级中的电源轨被充电到管线电源的第一电压电位。 在第一电源门控模式中，电力轨被充电到低于第一电压电位的阈值电压以减少泄漏。 在第二电源门控模式下，电源轨与第一电压电位分离。 电源门控第三管线级具有其电源轨或者耦合到第一电压电势或电源门控，其电源轨与第一电压电势分离。 第二电力门控管道阶段的电力轨道在第三电力门控管道阶段之前充电到第一电压电位。