公开(公告)号：US20110259012A1

公开(公告)日：2011-10-27

申请号：US13046229

申请日：2011-03-11

申请人： Hiroyuki TADA ,  Masato ASAHARA ,  Yoshihiro UEDA ,  Eiji SATO ,  Akira MINOURA

发明人： Hiroyuki TADA ,  Masato ASAHARA ,  Yoshihiro UEDA ,  Eiji SATO ,  Akira MINOURA

IPC分类号： F01N3/00

CPC分类号： F01N3/055 ,  F01P5/06 ,  F01P2001/005 ,  F01P2060/16 ,  Y02T10/20

摘要： A working vehicle has a cooling fan provided on a first side of an engine to blow air to the engine; a muffler main body provided on a second side thereof in a position lower than an upper surface of a head cover of the engine; and an exhaust pipe exposed in a position facing an air blowing path of the cooling fan higher than the upper surface of the head cover of the engine to discharge exhaust from the muffler main body.

摘要翻译： 工作车辆具有设置在发动机的第一侧上以将空气吹送到发动机的冷却风扇; 消声器主体，其设置在比所述发动机的头罩的上表面低的位置的第二侧上; 以及排气管，其在与所述发动机的头罩的上表面相比高于所述冷却风扇的空气吹送路径的位置处露出，以从所述消声器主体排出排气。

公开(公告)号：US20100073992A1

公开(公告)日：2010-03-25

申请号：US12559311

申请日：2009-09-14

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

摘要： A semiconductor memory device includes a memory cell having a first resistance state and a second resistance state, a bit line connected to the memory cell, a reference cell fixed to the first resistance state, a reference bit line connected to the reference cell, and a generation circuit configured to generate a reading voltage and a reference voltage. The generation circuit includes a constant current source connected to a first node, a first replica cell connected between the first node and a second node and fixed to the first resistance state, a second replica cell connected between the second node and a third node and fixed to the second resistance state, a first resistance element connected between the first node and a fourth node, and a second resistance element connected between the fourth node and the third node.

摘要翻译： 半导体存储器件包括具有第一电阻状态和第二电阻状态的存储单元，连接到存储单元的位线，固定到第一电阻状态的参考单元，连接到参考单元的参考位线，以及 所述发生电路被配置为产生读取电压和参考电压。 所述生成电路包括连接到第一节点的恒流源，连接在所述第一节点和第二节点之间并固定到所述第一电阻状态的第一副本单元，连接在所述第二节点和第三节点之间并固定的第二副本单元 连接到第二电阻状态，连接在第一节点和第四节点之间的第一电阻元件以及连接在第四节点和第三节点之间的第二电阻元件。

公开(公告)号：US20100067283A1

公开(公告)日：2010-03-18

申请号：US12624103

申请日：2009-11-23

申请人： Yoshihiro UEDA ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

发明人： Yoshihiro UEDA ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

IPC分类号： G11C7/08 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16

CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/12 ,  G11C11/1673 ,  G11C16/0491 ,  G11C16/26 ,  G11C17/126 ,  G11C2207/002 ,  G11C2207/063

摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

摘要翻译： 根据本发明的示例的读出放大器具有触发器连接的第一，第二，第三和第四FET。 第五FET的漏极连接到第一输入节点，并且其源极连接到电源节点。 第六FET的漏极连接到第二输入节点，其源极连接到电源节点。 通过用第一电流从第一输入节点充电第一输出节点并且通过用第二电流从第二输入节点对第二输出节点充电来启动感测操作。 开始感测操作后，第五和第六FET导通。

公开(公告)号：US20090323395A1

公开(公告)日：2009-12-31

申请号：US12409958

申请日：2009-03-24

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/10

CPC分类号： G11C11/56 ,  G11C13/00 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5631 ,  G11C2213/72

摘要： A plurality of memory cells, each including a variable resistance element capable of having four or more values, are arranged at intersections of first wirings and second wirings. A control circuit selectively drives the first and second wirings. A sense amplifier circuit compares, with a reference voltage, a voltage generated by a current flowing through a selected memory cell. A reference voltage generation circuit includes: a resistance circuit including first and second resistive elements connected in parallel. Each of the first resistive elements has a resistance value substantially the same as a maximum resistance value in the variable resistance elements, and each of the second resistive elements has a resistance value substantially the same as a minimum resistance value in the variable resistance elements. A current regulator circuit averages currents flowing through the first and second resistive elements.

摘要翻译： 在第一布线和第二布线的交点处布置有多个存储单元，每个存储单元包括能够具有四个或更多个值的可变电阻元件。 控制电路选择性地驱动第一和第二布线。 读出放大器电路与参考电压比较由流过所选存储单元的电流产生的电压。 参考电压产生电路包括：电阻电路，包括并联连接的第一和第二电阻元件。 每个第一电阻元件具有与可变电阻元件中的最大电阻值基本相同的电阻值，并且每个第二电阻元件具有与可变电阻元件中的最小电阻值基本相同的电阻值。 电流调节器电路平均流过第一和第二电阻元件的电流。

公开(公告)号：US20090091969A1

公开(公告)日：2009-04-09

申请号：US12244036

申请日：2008-10-02

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C11/02 ,  G11C11/409

CPC分类号： G11C5/147 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/79

摘要： A resistance change memory includes a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state, a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to the second resistance state, and is fixed in the first resistance state, and a first constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node.

摘要翻译： 电阻变化存储器包括连接到第一节点并被编程从第一电阻状态到第二电阻状态的存储单元，连接到第二节点的第一复制单元从第一节点产生用于编程的写入电压 电阻状态到第二电阻状态，并且被固定在第一电阻状态，以及连接到第二节点的第一恒流源，其中当将第二电阻状态写入存储单元时，保持第一节点的电压 等于第二个节点。

公开(公告)号：US20090034320A1

公开(公告)日：2009-02-05

申请号：US12183537

申请日：2008-07-31

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C11/416

CPC分类号： G11C13/0069 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/79

摘要： A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and apply a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state.

摘要翻译： 电阻变化存储器包括根据写入信息具有高电阻状态和低电阻状态的电阻变化元件，以及写入电路，被配置为提供写入电流，使得流过电阻变化元件的写入电流保持恒定 在电阻变化元件从高电阻状态变为低电阻状态之前和之后，并施加施加到电阻变化元件上的写入电压在电阻变化元件变化之前和之后保持恒定的写入电压 低电阻状态到高电阻状态。

公开(公告)号：US20080315335A1

公开(公告)日：2008-12-25

申请号：US12138942

申请日：2008-06-13

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  G11C11/16

摘要： A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a second length in a second direction. The second length is equal to or greater than the first length. A ratio of the second length to the first length is a first value. The second magnetoresistive effect element is used to determine a resistance state of the first magnetoresistive effect element. A shape of the second magnetoresistive effect element has a third length in a third direction and a fourth length in a fourth direction. The fourth length is equal to or greater than the third length. A ratio of the fourth length to the third length is a second value which is greater than the first value.

摘要翻译： 磁阻随机存取存储器包括第一和第二磁阻效应元件。 第一磁阻效应元件的形状在第一方向具有第一长度，在第二方向上具有第二长度。 第二长度等于或大于第一长度。 第二长度与第一长度的比率是第一值。 第二磁阻效应元件用于确定第一磁阻效应元件的电阻状态。 第二磁阻效应元件的形状在第三方向上具有第三长度，在第四方向上具有第四长度。 第四长度等于或大于第三长度。 第四长度与第三长度的比率是大于第一值的第二值。