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159 条记录 (耗时 0.035 秒)

    Magnetic memory
    22.
    发明授权
    Magnetic memory 有权
    磁记忆

    公开(公告)号：US06717845B2

    公开(公告)日：2004-04-06

    申请号：US10345253

    申请日：2003-01-16

    申请人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

    发明人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

    IPC分类号： G11C1115

    CPC分类号： G11C11/16

    摘要： A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first wiring extending in a first direction on or below the magnetoresistance effect element; a covering layer provided at least both sides of the first wiring, the covering layer being made of magnetic material, and the covering layer having a uniaxial anisotropy in the first direction along which a magnetization of the covering layer occurs easily; and a writing circuit configured to pass a current through the first wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

    摘要翻译： 磁存储器包括：具有磁记录层的磁阻效应元件; 在所述磁阻效应元件上或第二方向上延伸的第一布线; 所述覆盖层至少设置在所述第一布线的两侧，所述覆盖层由磁性材料制成，所述覆盖层在容易发生所述覆盖层的磁化的第一方向上具有单轴各向异性; 以及写入电路，被配置为使电流通过第一布线，以便通过由电流产生的磁场将信息记录在磁记录层中。

    Feeder for chip components
    24.
    发明授权
    Feeder for chip components 有权
    芯片组件馈线

    公开(公告)号：US06705819B1

    公开(公告)日：2004-03-16

    申请号：US09678096

    申请日：2000-10-04

    申请人： Akira Nemoto ,  Shigeki Takahashi ,  Nihei Kaishita ,  Mitsuhiro Namura

    发明人： Akira Nemoto ,  Shigeki Takahashi ,  Nihei Kaishita ,  Mitsuhiro Namura

    IPC分类号： B65B2102

    CPC分类号： B65G23/38 ,  B65G27/12 ,  B65G47/06 ,  H05K13/022

    摘要： A feeder for chip components is provided wherein the chip components can be supplied with high stability even in high-speed operation by operating a conveying member at a lower speed than that of a chip mounter and operating the conveying member even when the chip mounter is stopped. The chip components on a belt are supplied in one direction by lowering a feed lever according to the input load from a chip mounter so as to drive the belt connected to the feed lever via a transmission mechanism intermittently in one direction. urging means is provided for urging the feed lever in the returning direction by storing the input load of the chip mounter as energy while an eddy current damper is provided for delaying the returning operation of the feed lever relative to the returning operation of the chip mounter. When the chip mounter operates downwardly, the feed lever is moved downwardly by linking to the chip mounter while the conveyor belt is maintained in a stationary state. When the chip mounter operates upwardly, the feed lever is moved upwardly so as to be delayed relative to the chip mounter by the eddy current damper while the belt is driven at a low speed.

    摘要翻译： 提供了一种用于芯片部件的馈线，其中即使在高速操作中，即使在芯片安装器停止时，也可以以比芯片安装器低的速度操作输送部件并操作输送部件，可以提供高稳定性的芯片部件 。 通过根据来自芯片安装器的输入负载降低进给杆，沿着一个方向间歇地驱动通过传动机构驱动连接到进给杆的皮带，从而沿一个方向供给皮带上的切屑部件。 提供推动装置，用于通过将芯片安装机的输入负载作为能量存储来提供馈送杆，同时设置涡流阻尼器以延迟馈送杆相对于芯片安装机的返回操作的返回操作。 当芯片安装器向下操作时，馈送杆通过连接到芯片安装器而向下移动，同时传送带保持在静止状态。 当芯片安装器向上操作时，馈送杆向上移动，以便当带子以低速驱动时，通过涡流阻尼器相对于芯片安装器延迟。

    Apparatus and method for aligning parts
    25.
    发明授权
    Apparatus and method for aligning parts 失效
    对准零件的装置和方法

    公开(公告)号：US06691855B1

    公开(公告)日：2004-02-17

    申请号：US09097013

    申请日：1998-06-15

    申请人： Shigeki Takahashi ,  Nihei Kaishita

    发明人： Shigeki Takahashi ,  Nihei Kaishita

    IPC分类号： B65G4714

    CPC分类号： H05K13/028 ,  B65G47/1407

    摘要： There is disclosed a part-aligning apparatus that is simple in structure, less damages chip parts, and operates well even if its chip discharge passage is clogged or overflows. The apparatus has a part-holding chamber for accommodating a number of chip parts. An arc-shaped chute groove is formed in the inner surface of the bottom of the part-holding chamber to orient the chip parts in a given direction and to guide the sliding chips. A gate port is formed at the lower end of the chute groove to pass the sliding chip parts one by one. The discharge passage is formed tangent to the chute groove to align the passed chip parts in a row and to deliver them. Claw portions for removing clogging are formed on the inner surface of a rotary drum that forms the part-holding chamber. The claw portions urge any chip part halted in the gate port in an abnormal posture toward an opposite direction different from the direction in which the chips are delivered.

    摘要翻译： 公开了一种结构简单，损坏芯片部件的部件对齐装置，即使其芯片排出通道堵塞或溢出也能够良好地运行。 该装置具有容纳多个芯片部件的部分保持室。 在所述部件保持室的底部的内表面上形成有弧形的斜槽，以使所述芯片部件沿给定方向定向并引导所述滑动芯片。 在滑槽的下端形成有一个门口，一个接一个地通过滑动片。 排出通道形成为与滑槽相切，以使经过的芯片部分成一排排列并将其输送。 在形成部分保持室的旋转鼓的内表面上形成用于除去堵塞的爪部。 爪部将异常姿势的任何芯片部分阻止在门口中的任何芯片部分朝向与输送芯片的方向不同的相反方向。

    Apparatus for transporting parts
    27.
    发明授权
    Apparatus for transporting parts 有权
    运输零件的装置

    公开(公告)号：US06338608B1

    公开(公告)日：2002-01-15

    申请号：US09307772

    申请日：1999-05-10

    申请人： Shigeki Takahashi ,  Nihei Kaishita ,  Akira Nemoto

    发明人： Shigeki Takahashi ,  Nihei Kaishita ,  Akira Nemoto

    IPC分类号： B65G5912

    CPC分类号： H05K13/0434

    摘要： A part transporting apparatus comprises a guiding groove for lining up parts in one row and guiding the parts; a transporting member which is provided at the base of the guiding groove and transports the parts in a forward direction by itself moving forwards and backwards along the groove; and a driving means for reciprocally driving the transporting member in the forward and backward directions; wherein the transporting member is advanced slowly and retracted rapidly, so as to transport the parts forwards. Provided to this arrangement are: a stopper which operates so as to open and close in the width direction of the guiding groove, and hold the second part from the front of the row of parts being transported on the upper plane of the transporting member; and a shutter for opening and closing at the tip of the guiding groove, so as to cover the space above the first part in the row so as to prevent the part from flying out. The shutter is opened synchronously with the transporting member immediately before forward movement of the transporting member is completed, thereby extracting the first part separated from the second part. Such an arrangement provides for an apparatus for transporting parts, wherein the first part and second part can be separated in a sure manner even in the event that the parts are non-magnetic material, and wherein ease and stability of extracting of the first part is facilitated.

    摘要翻译： 一部分输送装置包括用于排列一排中的部分并引导部分的引导槽; 传送构件，其设置在引导槽的基部并通过其沿着槽向前和向后沿向前方向传送部件; 以及用于沿前后方向往复驱动传送部件的驱动装置; 其中传送构件缓慢前进并且迅速地缩回，以便将部件向前运送。 提供这样一种装置：一个在引导槽的宽度方向上打开和关闭的止动器，并且从传送部件的上平面上被传送的部分行的前部保持第二部分; 以及用于在引导槽的顶端打开和关闭的挡板，以便覆盖行中的第一部分上方的空间，以防止该部件飞出。 在完成传送部件的向前移动之前，快门与传送部件同步地打开，从而提取与第二部分分离的第一部分。 这种布置提供了用于运输部件的装置，其中即使在部件是非磁性材料的情况下，第一部分和第二部分可以以可靠的方式分离，并且其中第一部分的提取的容易性和稳定性是 方便了

    Production method of a vertical type MOSFET
    28.
    发明授权
    Production method of a vertical type MOSFET 失效
    垂直型MOSFET的制造方法

    公开(公告)号：US6015737A

    公开(公告)日：2000-01-18

    申请号：US515176

    申请日：1995-08-15

    申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

    发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

    IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/045 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/4236

    摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

    摘要翻译： 垂直型功率MOSFET可显着降低每个区域的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

    Manufacturing method of semiconductor device
    29.
    发明授权
    Manufacturing method of semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US5776812A

    公开(公告)日：1998-07-07

    申请号：US413410

    申请日：1995-03-30

    申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

    发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

    IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/0696 ,  H01L29/045 ,  H01L29/7813 ,  H01L29/4236

    摘要： A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer. After the double diffusion, a gate electrode is formed through a gate oxide film and a source electrode and a drain electrode are formed.

    摘要翻译： 一种MOSFET的制造方法，其具有在槽的侧面上的通道部分，其不允许将缺陷或污染物引入通道部分中并且可以使槽的形状均匀。 在n +型半导体衬底的主表面上形成具有低杂质浓度的n型外延层。 该表面被指定为主表面，并且化学干蚀刻被施加到该主表面的指定区域。 包括通过化学干蚀刻生成的表面的区域被选择性地氧化以形成具有特定厚度的选择性氧化膜。 在该过程之后，p型和n型杂质从主表面双重扩散以限定通道的长度并形成基层和源层。 此外，n +型半导体衬底被指定为漏极层。 在双扩散之后，通过栅极氧化膜形成栅电极，形成源电极和漏电极。