公开(公告)号：US20070085115A1

公开(公告)日：2007-04-19

申请号：US11308612

申请日：2006-04-12

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

IPC: H01L31/113 ,  H01L31/062 ,  H01L21/84 ,  H01L21/00

CPC classification number: H01L27/1214 ,  H01L29/40117 ,  H01L29/66833

Abstract: A memory cell, suitable for being disposed on a substrate, comprises a poly-Si island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-Si island is disposed on the substrate and includes a source doped region, a drain doped region and a channel region there-between. The first dielectric layer is disposed on the poly-Si island, the trapping layer is disposed on the first dielectric layer, the second dielectric layer is disposed on the trapping layer and the control gate is disposed on the second dielectric layer. The above-described memory cell can be integrated into the manufacturing process of a low temperature polysilicon LCD panel (LTPS LCD panel) or an organic light emitting display panel (OLED panel).

Abstract translation: 适用于设置在基板上的存储单元包括多晶硅岛，第一介电层，俘获层，第二介电层和控制栅。 多晶硅岛设置在衬底上，包括源极掺杂区，漏极掺杂区和其间的沟道区。 第一介电层设置在多晶硅岛上，俘获层设置在第一介电层上，第二介电层设置在俘获层上，控制栅设置在第二介质层上。 上述存储单元可以集成到低温多晶硅LCD面板（LTPS LCD面板）或有机发光显示面板（OLED面板）的制造过程中。

公开(公告)号：US07161226B2

公开(公告)日：2007-01-09

申请号：US11131084

申请日：2005-05-17

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: H01L29/00

CPC classification number: H01L23/5221 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Abstract translation: 一种多层导线结构，包括：基板，形成在第一层上的多个第一导电线，该第一导电线在基板上沿着第一方向彼此平行地延伸;多个第二导电线，形成在第一层上的第一层 在与第一方向正交的第二方向上彼此平行地延伸的多个第三导线组，所述第二导电线形成在第一方向上延伸，每组第三导线对应于第一导线之一， 以及形成在所述第一层和所述第二层之间的多组导电路径，每组导电路径对应于所述第一导电线中的一条和一组第三导电线，并将相应的第一导电线电连接到相应的集合 的第三导线。

公开(公告)号：US20060172469A1

公开(公告)日：2006-08-03

申请号：US11312473

申请日：2005-12-21

Applicant: Jia-Xing Lin ,  Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Jia-Xing Lin ,  Yu-Cheng Chen ,  Chi-Lin Chen

IPC: H01L21/84 ,  H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

Abstract: An amorphous silicon (a-Si) layer is first formed on a substrate, and the a-Si layer is next patterned to form silicon islands for defining device active regions. Then, a single shot laser beam with long pulse is utilized to irradiate each silicon island, and lateral growth crystallization is induced in each silicon island for transforming a-Si into polycrystalline silicon (poly-Si). Finally, the general subsequent processes for thin film transistor (TFT) fabrication are performed in turn to fabricate poly-Si TFTs.

Abstract translation: 首先在衬底上形成非晶硅（a-Si）层，然后将a-Si层图案化以形成用于限定器件有源区的硅岛。 然后，利用具有长脉冲的单次激光束照射每个硅岛，并且在每个硅岛中诱导横向生长结晶以将a-Si转化为多晶硅（poly-Si）。 最后，依次进行薄膜晶体管（TFT）制造的一般后续处理以制造多晶硅TFT。

公开(公告)号：US20060088986A1

公开(公告)日：2006-04-27

申请号：US11222804

申请日：2005-09-12

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Po-Hao Tsai

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Po-Hao Tsai

IPC: H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1281 ,  H01L29/66757

Abstract: An amorphous silicon layer and at least a heat-retaining layer are formed on a substrate in turn. Wherein, the heat-retaining layer is controlled to have an anti-reflective thickness for reducing the threshold laser energy to effect the melting of the amorphous silicon layer. Then, a laser irradiation process is performed to transform the amorphous silicon layer into a polycrystalline silicon layer. During the laser irratiation process, a portion of the laser energy transmits the heat-retaining layer to effect the melting of the amorphous silicon layer, and another portion of the laser energy is absorbed by the heat-retaining layer.

Abstract translation: 依次在基板上形成非晶硅层和至少一个保温层。 其中，保温层被控制为具有用于降低阈值激光能量以实现非晶硅层熔化的抗反射厚度。 然后，执行激光照射处理以将非晶硅层转变成多晶硅层。 在激光照射过程中，激光能量的一部分透过保温层来实现非晶硅层的熔化，另一部分激光能被保温层吸收。

公开(公告)号：US20060043072A1

公开(公告)日：2006-03-02

申请号：US11194314

申请日：2005-08-01

Applicant: Yu-Cheng Chen ,  Jia-Xing Lin ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Jia-Xing Lin ,  Chi-Lin Chen

IPC: C03C15/00

CPC classification number: H01L21/02675 ,  C03C15/00 ,  C03C15/02 ,  C03C23/0025 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L21/32115 ,  H01L29/6675 ,  H01L29/78606

Abstract: A method for planarizing polysilicon comprises providing a substrate, forming a dielectric layer on the substrate, forming an amorphous silicon film on the dielectric layer, etching the amorphous silicon film to remove native oxide formed on a surface of the amorphous silicon film, exposing the surface of the amorphous silicon film to a first radiation source to polycrystallize the amorphous silicon film into a polysilicon film, etching the polysilicon film to remove weak bonded silicon formed on a surface of the polysilicon film, and exposing the surface of the polysilicon film to a second radiation source to reflow the polysilicon film.

Abstract translation: 一种用于平坦化多晶硅的方法包括：提供衬底，在衬底上形成电介质层，在电介质层上形成非晶硅膜，蚀刻非晶硅膜以去除在非晶硅膜的表面上形成的自然氧化物， 将所述非晶硅膜施加到第一辐射源以将所述非晶硅膜多晶化为多晶硅膜，蚀刻所述多晶硅膜以去除在所述多晶硅膜的表面上形成的弱键合硅，并将所述多晶硅膜的表面暴露于第二 辐射源来回流多晶硅膜。

公开(公告)号：US20050136612A1

公开(公告)日：2005-06-23

申请号：US10780589

申请日：2004-02-19

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/336 ,  H01L29/786 ,  H01L21/76

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L21/268 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

Abstract: An amorphous silicon layer is formed on a substrate, and then a protective layer and a reflective layer are formed in turn to form a film stack on portions of the amorphous silicon layer. The reflective layer is a metal material with reflectivity of laser, and the protective layer is able to prevent metal diffusion. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer under the film stack of the protective layer and the reflective layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer to form poly-silicon having crystal grains with size of micrometers and high grain order.

Abstract translation: 在基板上形成非晶硅层，然后依次形成保护层和反射层，以在非晶硅层的部分上形成膜堆叠。 反射层是具有激光反射率的金属材料，保护层能够防止金属扩散。 当准分子激光器加热非晶硅层以使非晶硅结晶时，在保护层和反射层的膜堆叠下面的非晶硅层中形成成核位置。 接下来，在非晶硅层中发生横向膨胀结晶，形成晶粒大小为微米，晶粒度高的多晶硅。

公开(公告)号：US20050073619A1

公开(公告)日：2005-04-07

申请号：US10687759

申请日：2003-10-20

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: G09F9/30 ,  G02F1/1362 ,  H01L23/522 ,  H01L27/12 ,  G02F1/136

CPC classification number: H01L27/12 ,  G02F1/136286 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered complementary wire structure and a manufacturing method thereof are disclosed, comprising a first wire and a second wire. Each of the first and the second wires comprises a main line and a plurality of branch lines located in a different layer from the main line. A plurality contact holes are formed in an insulating layer between the first wire and the second wire to connect the main line of the first wire and the branch lines of the first wire, and connect the main line of the second wire and the branch lines of the second wire. The main line of the first wire is insulated and crossed with the main line of the second wire. The main line of the first wire and the branch lines of the second wire are insulated with each other and located in the same layer. The main line of the second wire and the branch lines of the first wire are insulated with each other and located in the same layer.

Abstract translation: 公开了一种多层互补线结构及其制造方法，包括第一线和第二线。 第一和第二导线中的每一个包括主线和位于与主线不同的层中的多个分支线。 在第一线和第二线之间的绝缘层中形成多个接触孔，以连接第一线的主线和第一线的分支线，并将第二线的主线和 第二根线。 第一根导线的主线绝缘并与第二根导线的主线交叉。 第一线的主线和第二线的分支线彼此绝缘并位于同一层中。 第二线的主线和第一线的分支线彼此绝缘并位于同一层中。

公开(公告)号：US08570480B2

公开(公告)日：2013-10-29

申请号：US12410475

申请日：2009-03-25

Applicant: Yi-Chen Chiang ,  Chih-Hung Shih ,  Maw-Song Chen ,  Tzu-Wei Ho ,  Ching-Huan Lin ,  Yu-Hsuan Li ,  Yao-Jen Hsieh ,  Ya-Ting Hsu ,  Chi-Mao Hung ,  Ken-Ming Chen ,  Yu-Cheng Chen

Inventor： Yi-Chen Chiang ,  Chih-Hung Shih ,  Maw-Song Chen ,  Tzu-Wei Ho ,  Ching-Huan Lin ,  Yu-Hsuan Li ,  Yao-Jen Hsieh ,  Ya-Ting Hsu ,  Chi-Mao Hung ,  Ken-Ming Chen ,  Yu-Cheng Chen

IPC: G02F1/1345 ,  G09G3/36 ,  G06F3/038

CPC classification number: G09G3/3648 ,  G02F1/1345 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0232 ,  G09G2310/0278

Abstract: A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.

Abstract translation: 公开了一种具有纤细边框结构的显示装置。 显示装置包括基板，多条数据线，多条栅极线，多条辅助栅极线和驱动模块。 基板包括显示区域和边界区域。 数据线，栅极线和辅助栅极线设置在显示区域中。 驱动模块设置在边界区域。 栅极线与数据线垂直交叉。 辅助栅极线与数据线并联。 每个辅助栅极线电连接到一个对应的栅极线。 数据和辅助栅极线基于交错布置电连接到驱动模块。 另外公开了一种驱动方法，用于通过辅助栅极线将由驱动模块提供的栅极信号传送到栅极线。

公开(公告)号：US08553193B2

公开(公告)日：2013-10-08

申请号：US12909831

申请日：2010-10-22

Applicant: Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen ,  Tsan-Chun Wang

Inventor： Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen ,  Tsan-Chun Wang

IPC: G02F1/1343

CPC classification number: G02F1/13624 ,  G02F2001/13606

Abstract: A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.

Abstract translation: 像素结构包括第一和第二扫描线，数据线，覆盖第一和第二扫描线的第一绝缘层和数据线的一部分并具有凹部，覆盖第一绝缘层的第二绝缘层， 覆盖数据线和凹部的电容器电极线，电容器电极线上的第三绝缘层，与第二扫描线和数据线电连接的第一有源器件，与第一有源器件电连接的第二有源器件， 第一扫描线以及分别电连接到第一和第二有源器件的第一和第二像素电极。 数据线和第一和第二扫描线的部分在同一层中。 凹槽位于数据线部分的两侧。

公开(公告)号：US08541750B2

公开(公告)日：2013-09-24

申请号：US12553982

申请日：2009-09-03

Applicant: Yu-Cheng Chen ,  An-Thung Cho ,  Ching-Sang Chuang ,  Chia-Tien Peng

Inventor： Yu-Cheng Chen ,  An-Thung Cho ,  Ching-Sang Chuang ,  Chia-Tien Peng

IPC: G01T1/20

CPC classification number: H01L31/085

Abstract: A structure of X-ray detector includes a Si-rich dielectric material for serving as a photo-sensing layer to increase light sensitivity. The fabrication method of the X-ray detector including the Si-rich dielectric material needs less photolithography-etching processes, so as to reduce the total thickness of thin film layers and decrease process steps and cost.

Abstract translation: X射线检测器的结构包括用作光敏层的富Si介电材料以增加光敏度。 包含富Si介电材料的X射线检测器的制造方法需要较少的光刻蚀刻工艺，以减少薄膜层的总厚度并降低工艺步骤和成本。