公开(公告)号：US20190278736A1

公开(公告)日：2019-09-12

申请号：US16298373

申请日：2019-03-11

Applicant: Analog Devices Global Unlimited Company

Inventor： David AHERNE ,  Jofrey SANTILLAN ,  Wes Vernon LOFAMIA ,  Paul O'SULLIVAN ,  Padraig McDAID

IPC: G06F13/42

Abstract: SPI Round Robin Mode for Single-Cycle MUX Channel Sequencing. SPI round robin mode is an SPI mode applicable for MUX devices control. It allows the MUX output to connect to the next input channel sequentially in just one clock cycle. Configurations can be made such as: clock edge to use (rising/falling), ascending/descending channel sequence, and enabling/disabling the channels to go through. The device supersedes an ADC with built in sequencing and is applicable to multiplexing, switching, instrumentation, process control and isolation application—while retaining SPI device control and operation.

公开(公告)号：US10367411B2

公开(公告)日：2019-07-30

申请号：US15849047

申请日：2017-12-20

Applicant: Analog Devices Global Unlimited Company

Inventor： Francis Martin

IPC: H02M7/04 ,  H02M1/42 ,  G05F1/70 ,  H02M1/32 ,  H02M7/219 ,  H02M3/337

Abstract: A power factor correction device for providing tolerance to a fault condition in an input supply can include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit can interleave operation of the first boost circuit and operation of the second boost circuit such as to generate an output voltage when the input supply is received at the power factor correction device. The controller circuit can route, in response to the fault condition, a stored supply of the second boost circuit to an input of the first boost circuit. The controller circuit can control the first boost circuit to maintain the output voltage.

公开(公告)号：US10361711B1

公开(公告)日：2019-07-23

申请号：US16219198

申请日：2018-12-13

Applicant: Analog Devices International Unlimited Company

Inventor： Shanthi Pavan Yendluri ,  Hajime Shibata ,  Christopher W. Mangelsdorf

IPC: H03M1/12 ,  H03M1/10 ,  H03M1/06 ,  H03M1/18 ,  H03M1/00

Abstract: Residue generation systems for use in continuous-time and hybrid ADCs are disclosed. An example residue generation system includes at least one stub filter, configured to generate a modified analog input based on an analog input, and a quantizer, configured to generate a digital input to a feedforward DAC based on the modified analog input generated by the filter. The feedforward DAC is configured to generate a feedforward path analog output based on the digital input generated by the quantizer, and the system may further be configured to generate a residue signal based on the feedforward path analog output. Providing one or more stub filters that filter the analog input before it is quantized by the quantizer advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer.

公开(公告)号：US10348250B2

公开(公告)日：2019-07-09

申请号：US15790793

申请日：2017-10-23

Applicant: Analog Devices Global Unlimited Company

Inventor： Dennis A. Dempsey

IPC: H03F1/26 ,  H03F1/02 ,  H03F1/42 ,  H03M1/66

Abstract: The noise power of an amplifier or buffer can increase towards the unity gain crossover frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.

公开(公告)号：US10346273B2

公开(公告)日：2019-07-09

申请号：US15713090

申请日：2017-09-22

Applicant: Analog Devices Global Unlimited Company

Inventor： Courtney E. Fricano ,  Paul P. Wright ,  David Brownell

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3183 ,  G06F17/50

Abstract: Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.

公开(公告)号：US10310476B2

公开(公告)日：2019-06-04

申请号：US15958871

申请日：2018-04-20

Applicant: Analog Devices Global Unlimited Company

Inventor： Navdeep Singh Dhanjal ,  Shengbing Zhou

IPC: H03K19/173 ,  G05B19/045 ,  G06F1/3296 ,  H03K19/00 ,  G06F12/0817

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

公开(公告)号：US10277433B1

公开(公告)日：2019-04-30

申请号：US15813905

申请日：2017-11-15

Applicant: Analog Devices Global Unlimited Company

Inventor： Jacobo Riesco-Prieto ,  Philip Curran ,  Michael McCarthy

IPC: H04L1/00 ,  H04L25/08 ,  H04L25/49 ,  H04L27/00

Abstract: This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

公开(公告)号：US10164614B2

公开(公告)日：2018-12-25

申请号：US15087723

申请日：2016-03-31

Applicant: Analog Devices Global Unlimited Company

Inventor： Xin Yang ,  Tianting Zhao ,  Baoxing Chen

IPC: H03B5/12 ,  H03K3/013 ,  H03B5/08

Abstract: Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

公开(公告)号：US10148263B2

公开(公告)日：2018-12-04

申请号：US15216498

申请日：2016-07-21

Applicant: Analog Devices Global Unlimited Company

Inventor： Edward John Coyne ,  Patrick Martin McGuinness ,  William Allan Lane ,  Laurence O'Sullivan

IPC: H01L29/66 ,  H03K17/795 ,  H03K19/003 ,  H03K17/567 ,  H01L27/06 ,  H02M7/217 ,  H02M7/537 ,  H02P27/06 ,  H03K17/06

Abstract: A combined isolator and power switch is disclosed. Such devices are useful in isolating low voltage components such as control compilers from motors or generators working at high voltages. The combined isolator and power switch includes circuits to transfer internal power from its low voltage side to the switch driver circuits on the high voltage side. The combined isolator and switch is compact and easy to use.

公开(公告)号：US12080460B2

公开(公告)日：2024-09-03

申请号：US17890163

申请日：2022-08-17

Applicant: Analog Devices Global Unlimited Company

Inventor： Paul Lambkin ,  Patrick J. Murphy ,  Bernard Patrick Stenson ,  Laurence B. O'Sullivan ,  Stephen O'Brien ,  Shane Geary ,  Baoxing Chen ,  Sombel Diaham

IPC: H01F19/08 ,  H01G2/00 ,  H04B1/04 ,  H04B1/16

CPC classification number: H01F19/08 ,  H01F2019/085 ,  H01G2/00 ,  H04B1/04 ,  H04B1/16

Abstract: A micro-isolator is described. The micro-isolator may include a first isolator element, a second isolator element, and a first dielectric material separating the first isolator element from the second isolator element. A second dielectric material may completely or partly encapsulate the second isolator element, or may be present at outer corners of the second isolator element. The second dielectric material may have a larger bandgap than the first dielectric material, and its configuration may reduce electrostatic charge injection into the first dielectric material. The micro-isolator may be formed using microfabrication techniques.