公开(公告)号：US20180089338A1

公开(公告)日：2018-03-29

申请号：US15719449

申请日：2017-09-28

申请人： AUTODESK, INC.

发明人： Hyunmin CHEONG ,  Wei LI ,  Francesco IORIO

IPC分类号： G06F17/50 ,  G06N5/04

CPC分类号： G06F17/50 ,  G06F17/5095 ,  G06F2217/02 ,  G06N5/022 ,  G06N5/04

摘要： Embodiments of the invention disclosed herein provide techniques for generating a design autocomplete recommendation. The techniques include determining one or more first components included in a first design. The techniques further include analyzing, via the processor, a plurality of designs included in a database to select a second design that includes one or more second components that correspond to the one or more first components. The techniques further include selecting, via a processor, one or more third components included in the second design that are not included in the first design. The techniques further include causing an autocomplete recommendation that includes the one or more third components to be output.

公开(公告)号：US20180068044A1

公开(公告)日：2018-03-08

申请号：US15694749

申请日：2017-09-01

申请人： Synopsys, Inc.

发明人： Robert J. Erickson

IPC分类号： G06F17/50 ,  G06N3/12

CPC分类号： G06F17/5054 ,  G06F2217/02 ,  G06N3/126 ,  G06N5/022

摘要： A method for partitioning for a hypergraph including a plurality of nodes into a plurality of bins includes assigning each node of the hypergraph to one of the plurality of bins to generate a candidate solution, and for each pair of nodes in the candidate solution, calculating a weighted covariance based on the bin assignment of each node of the pairs of nodes in the candidate solution. The assigning and the calculating are repeated to generate an accumulated weighted covariance for the pairs of nodes, from which a seed partition of the hypergraph is generated.

公开(公告)号：US20180032639A1

公开(公告)日：2018-02-01

申请号：US15553059

申请日：2015-12-28

申请人： MISUMI CORPORATION

发明人： Rie NAKAGAWA ,  Taketo KUDO ,  Masatsugu TSUKAMOTO

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F2217/02 ,  G06Q30/0603 ,  G06Q50/04

摘要： A search is performed as to whether a modified component is stored in a standard component data memory unit in which data on a plurality of standard components each including at least dimensions that define the shape and a model number are prestored, and when it is found that the modified component is stored in the standard component data memory unit, the model number of the component before the modification is replaced with a model number related to the standard component.

公开(公告)号：US09852248B2

公开(公告)日：2017-12-26

申请号：US14856579

申请日：2015-09-17

申请人： Wallace W Lin

发明人： Wallace W Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/12

摘要： An integrated-circuit design tool system capable of minimizing a plasma induced charging effect to a transistor in a plasma-based process performed for a dielectric layer on a metal layer comprises a pre-processing unit, a charging evaluator engine, a charging eliminator engine, a post-processing unit, and a non-transitory computer readable medium.

公开(公告)号：US20170357741A1

公开(公告)日：2017-12-14

申请号：US15621895

申请日：2017-06-13

申请人： Brigham Young University

发明人： Mark S. Trent ,  Daniel Staves ,  Ammon Hepworth

IPC分类号： G06F17/50 ,  G06F9/50 ,  G06F13/26 ,  G06F17/30 ,  G06F11/14

CPC分类号： G06F17/5009 ,  G06F9/50 ,  G06F11/1448 ,  G06F11/1466 ,  G06F13/26 ,  G06F17/30368 ,  G06F17/50 ,  G06F2217/02

摘要： A method for loading an assembly for a CAx client includes determining referenced part IDs referenced by the assembly and for each referenced part ID, determining a latest applied command of saved checkpoints for each part file of a referenced part ID. The method further includes determining any unapplied commands for each referenced part ID, loading the part file for each referenced part ID with the latest applied command to the CAx client, and applying the unapplied commands sequentially by command number. A computer program product such as a computer readable medium and a computer system corresponding to the above method are also disclosed herein.

公开(公告)号：US09841207B2

公开(公告)日：2017-12-12

申请号：US14072110

申请日：2013-11-05

申请人： LG ELECTRONICS INC.

发明人： Jungyul Park ,  Sangeun Cho ,  Shinae Kang ,  Junmo Kim ,  Mingyu Park

IPC分类号： F24F11/00 ,  G06F17/50

CPC分类号： F24F11/0086 ,  F24F11/30 ,  G06F17/5004 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/34

摘要： Provided are an installation guide system for an air conditioner and a method of using the same. The installation guide system for an air conditioner may include a memory that stores at least one image for a building in which an air conditioner installed, and a display providing a user interface to design a disposition of the air conditioner in the building. The user interface may include a first region that provides a recommended configuration of indoor units to be installed based on a type of an indoor unit of the air conditioner or load information for a prescribed room in which the indoor unit is installed. The user interface may also include a second region that displays the stored image of the building and a graphical image for the indoor units in the image of the building based on the recommendations provided in the first region.

公开(公告)号：US20170293583A1

公开(公告)日：2017-10-12

申请号：US15448910

申请日：2017-03-03

申请人： MIE FUJITSU SEMICONDUCTOR LIMITED

发明人： Seiji Goto

IPC分类号： G06F13/40 ,  G06F17/50 ,  G06F13/36

CPC分类号： G06F13/4022 ,  G06F13/36 ,  G06F17/5072 ,  G06F2217/02 ,  G06F2217/84

摘要： A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. The semiconductor integrated circuit fixes the logic level of the test signal line adjacent to the bus signal line in the system mode that uses the bus signal line. The semiconductor integrated circuit fixes the logic level of the bus signal line adjacent to the test signal line in the scan mode that uses the test signal line.

公开(公告)号：US20170256100A1

公开(公告)日：2017-09-07

申请号：US15236697

申请日：2016-08-15

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Ji Hyung LEE ,  Jae Woo KIM ,  Man Hee LEE ,  Kyung Kyu KANG ,  Chang Joon PARK

IPC分类号： G06T19/20 ,  G06F17/50 ,  G06T17/10

CPC分类号： G06T19/20 ,  G06F17/5004 ,  G06F2217/02 ,  G06T17/10 ,  G06T2210/04 ,  G06T2219/2004

摘要： An apparatus and method for editing three-dimensional (3D) building data. The apparatus for editing the 3D building data includes an input unit configured to obtain 3D scan data of a building, and a processor configured to divide the obtained 3D scan data of the building in units of construction components.

公开(公告)号：US20170255734A1

公开(公告)日：2017-09-07

申请号：US15601707

申请日：2017-05-22

申请人： ARM Limited

发明人： Paul Christopher de Dood

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/02

摘要： The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology.

公开(公告)号：US09741802B2

公开(公告)日：2017-08-22

申请号：US14979915

申请日：2015-12-28

申请人： Sensor Electronic Technology, Inc.

发明人： Grigory Simin ,  Michael Shur ,  Remigijus Gaska

IPC分类号： H01L29/66 ,  H01L29/40 ,  G06F17/50 ,  H01L29/778 ,  H01L29/872 ,  H01L29/20

CPC分类号： H01L29/408 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/02 ,  G06F2217/78 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/7786 ,  H01L29/872

摘要： A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film or a low conductive film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film or the low conductive film. The conducting elements can vary in at least one of composition, doping, conductivity, size, thickness, shape, and distance from the device channel along a lateral length of the insulating film or the low conductive film, or in a direction that is perpendicular to the lateral length.