公开(公告)号：US07082179B2

公开(公告)日：2006-07-25

申请号：US10735336

申请日：2003-12-12

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03K21/00

CPC分类号： H03L7/0805 ,  H03K23/58 ,  H03L7/0814 ,  H03L7/089

摘要： A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode clock providing unit. The clock dividing unit receives a source clock of the DLL to generate a plurality of divided clocks, each having a period different from each other. The test mode clock providing unit selectively outputs the plurality of the divided clocks in a test mode in response to a test mode signal and a test mode period selecting signal. And, the normal mode clock providing unit outputs selected one of the plurality of the divided clocks in a normal mode in response to the test mode signal.

摘要翻译： DLL（延迟锁定环）的分频器由于过程，温度和电源电压的变化而测量各种周期的tAC，并且提供具有最佳tAC的分频时钟。 时钟分频器包括时钟分频单元，测试模式时钟提供单元和正常模式时钟提供单元。 时钟分割单元接收DLL的源时钟以产生多个具有彼此不同的周期的分割时钟。 测试模式时钟提供单元响应于测试模式信号和测试模式周期选择信号，以测试模式选择性地输出多个划分的时钟。 并且，正常模式时钟提供单元响应于测试模式信号以正常模式输出所选择的多个分频时钟之一。

公开(公告)号：US06741670B2

公开(公告)日：2004-05-25

申请号：US10134740

申请日：2002-04-29

申请人： David Tester

发明人： David Tester

IPC分类号： H03K2138

CPC分类号： H03K23/58 ,  H03K21/38

摘要： A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

摘要翻译： 计数器级通常包括触发器和复位电路。 触发器可以被配置为响应于施加到时钟输入的计数信号而在第一和第二状态之间切换触发器信号以实现计数操作。 复位电路可以被配置为在不改变触发器信号的状态的情况下将计数器级复位到预定状态。

公开(公告)号：US06181174B2

公开(公告)日：2001-01-30

申请号：US09404221

申请日：1999-09-23

申请人： Waichirou Fujieda ,  Yasuharu Sato ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

发明人： Waichirou Fujieda ,  Yasuharu Sato ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/133 ,  H03K23/58 ,  H03L7/0814

摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.

摘要翻译： 半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。 延迟系统包括延迟虚拟时钟的可变延迟电路。 控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。

公开(公告)号：US5086441A

公开(公告)日：1992-02-04

申请号：US484854

申请日：1990-02-26

申请人： Kousei Maemura ,  Hiroichi Ishida

发明人： Kousei Maemura ,  Hiroichi Ishida

IPC分类号： H03K21/38 ,  H03K23/00 ,  H03K23/58

CPC分类号： H03K21/38 ,  H03K23/58

摘要： A frequency divider circuit having N flip-flops connected in series, includes a logic circuit for monitoring at least one of the outputs of the N flip-flops and halting the frequency division operation of a prior stage flip-flop when the value of the output which is monitored is equal to a predetermined value when a reset signal is input, and restarting frequency division operation when the reset signal is cancelled.

公开(公告)号：US5060243A

公开(公告)日：1991-10-22

申请号：US530703

申请日：1990-05-29

申请人： Kim H. Eckert

发明人： Kim H. Eckert

IPC分类号： H03K21/12 ,  H03K21/40 ,  H03K23/58 ,  H03K23/66

CPC分类号： H03K21/12 ,  H03K21/40 ,  H03K23/58 ,  H03K23/665

摘要： An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

摘要翻译： 响应于输入时钟信号，异步波纹计数器从预定二进制值计数到零。 零检测逻辑耦合到纹波计数器，用于当计数器计数到零时，从纹波计数器的最高有效位到最低有效位检测。 计数器和零检测逻辑都接收并存储预定的二进制值。 从MSB到LSB的纹波计数器的数字监控可以防止纹波计数器中零状态的错误检测，并允许纹波计数器扩展到任意大量的位，而不会牺牲最大输入时钟频率。

公开(公告)号：US4443887A

公开(公告)日：1984-04-17

申请号：US272831

申请日：1981-06-12

申请人： Takami Shiramizu

发明人： Takami Shiramizu

IPC分类号： G10H5/00 ,  H03K21/00 ,  H03K23/00 ,  H03K23/58 ,  H03K23/64 ,  H03K23/66 ,  H03K21/36

CPC分类号： H03K23/58 ,  H03K21/12 ,  H03K23/665

摘要： A frequency-dividing circuit comprises an asynchronous counter having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each of the one-half frequency-dividers, where the asynchronous counter is set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when a load pulse is applied, a coincidence detection circuit for detecting the coincidence of a plurality of outputs supplied from the asynchronous counter, and a frequency-divided output signal and load pulse generation circuit supplied with the master clock signal and an output signal of the coincidence detection circuit, for generating a frequency-divided output signal and a load pulse. The frequency-divided output signal and load pulse generation circuit supplies a load pulse to the asynchronous counter.

摘要翻译： 分频电路包括具有多个半分频器的异步计数器，该多个分频器在多级中串联连接，其中主时钟信号被施加到初级的输入端，用于异步产生输出信号 其中异步计数器设置有预置数据n（n为整数）的半个分频器中的每一个，该预置数据是在施加负载脉冲时根据期望的分频比预设的，一致检测电路 检测从异步计数器提供的多个输出的一致性，以及提供有主时钟信号的分频输出信号和负载脉冲产生电路以及一致检测电路的输出信号，以产生分频输出信号 和负载脉冲。 分频输出信号和负载脉冲发生电路向异步计数器提供负载脉冲。

公开(公告)号：US3316426A

公开(公告)日：1967-04-25

申请号：US45113265

申请日：1965-04-27

申请人： SUWA SEISKOSHA KK

发明人： ISSEI IMAHASHI

IPC分类号： H03K3/286 ,  H03K23/58

CPC分类号： H03K3/286 ,  H03K23/58

公开(公告)号：US2954163A

公开(公告)日：1960-09-27

申请号：US40995054

申请日：1954-02-12

申请人： BURROUGHS CORP

发明人： OKADA ROBERT H

IPC分类号： H03K21/18 ,  H03K23/58

CPC分类号： H03K23/58 ,  H03K21/18

公开(公告)号：US11705836B2

公开(公告)日：2023-07-18

申请号：US17981768

申请日：2022-11-07

申请人： INTEVA PRODUCTS FRANCE SAS

发明人： François Breynaert ,  Simon Herpin

IPC分类号： H02P7/00 ,  H02P7/285 ,  H03K23/58

CPC分类号： H02P7/0094 ,  H02P7/2855 ,  H03K23/58

摘要： A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage delivered by the voltage supply. The rotation of the rotor 103 generates a mechanical force that drives a component. A ripple count circuit 104 is configured to filter the drive current based on a rotational speed (ω) of the rotor 103 to generate a filtered drive current signal, and to generate a varying threshold based on the filtered drive current signal. Based on a comparison between the filtered drive current signal and the varying threshold, the ripple count circuit 104 generates a pulsed output signal indicative of the rotational speed (ω) of the rotor and a rotational position (θ) of the rotor.

公开(公告)号：US20180183414A1

公开(公告)日：2018-06-28

申请号：US15841950

申请日：2017-12-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ta-Pen GUO ,  Chi-Lin LIU ,  Shang-Chih HSIEH ,  Jerry Chang-Jui KAO ,  Li-Chun TIEN ,  Lee-Chung LU

IPC分类号： H03K3/0233 ,  H03K23/58 ,  H01L27/02 ,  H03K3/01 ,  H03K19/094

CPC分类号： H03K3/02332 ,  H01L27/0207 ,  H01L27/0233 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879 ,  H03K3/01 ,  H03K3/356121 ,  H03K3/35625 ,  H03K19/094 ,  H03K23/58

摘要： A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.