公开(公告)号：US11107685B2

公开(公告)日：2021-08-31

申请号：US16474639

申请日：2018-02-01

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Keisuke Nakamura ,  Muneyoshi Suita ,  Akifumi Imai ,  Kenichiro Kurahashi ,  Tomohiro Shinagawa ,  Takashi Matsuda ,  Koji Yoshitsugu ,  Eiji Yagyu ,  Kunihiko Nishimura

IPC分类号： H01L23/00 ,  H01L21/70 ,  H01L21/18 ,  H01L21/76 ,  H01L21/02 ,  H01L21/447

摘要： The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.

公开(公告)号：US11094575B2

公开(公告)日：2021-08-17

申请号：US16429145

申请日：2019-06-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Chang-Chen Tsao

IPC分类号： H01L21/68 ,  H01L21/683 ,  H01L21/18 ,  H01L21/687

摘要： In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.

公开(公告)号：US11087971B2

公开(公告)日：2021-08-10

申请号：US16685577

申请日：2019-11-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yung-Lung Lin ,  Hau-Yi Hsiao ,  Chih-Hui Huang ,  Kuo-Hwa Tzeng ,  Cheng-Hsien Chou

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/306 ,  H01L21/20 ,  H01L21/18

摘要： The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.

公开(公告)号：US11059280B2

公开(公告)日：2021-07-13

申请号：US16356325

申请日：2019-03-18

申请人： EV Group E. Thallner GmbH

发明人： Thomas Wagenleitner ,  Markus Wimplinger ,  Friedrich Paul Lindner ,  Thomas Plach ,  Florian Kurz

IPC分类号： B32B38/18 ,  H01L21/18 ,  B32B37/00 ,  B32B37/18 ,  B32B37/10 ,  B29C65/78 ,  H01L21/67 ,  H01L21/683 ,  B29C65/00

摘要： A method for bonding a contact surface of a first substrate to a contact surface of a second substrate comprising of the steps of: positioning the first substrate on a first receiving surface of a first receiving apparatus and positioning the second substrate on a second receiving surface of a second receiving apparatus; establishing contact of the contact surfaces at a bond initiation site; and bonding the first substrate to the second substrate along a bonding wave which is travelling from the bond initiation site to the side edges of the substrates, wherein the first substrate and/or the second substrate is/are deformed for alignment of the contact surfaces.

公开(公告)号：US11037919B2

公开(公告)日：2021-06-15

申请号：US16919989

申请日：2020-07-02

申请人： Invensas Bonding Technologies, Inc.

发明人： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Guilian Gao ,  Gaius Gillman Fountain, Jr.

IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/18

摘要： Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

公开(公告)号：US20210118898A1

公开(公告)日：2021-04-22

申请号：US17113285

申请日：2020-12-07

申请人： Toshiba Memory Corporation

发明人： Yoshiaki FUKUZUMI ,  Hideaki AOCHI ,  Mie MATSUO ,  Kenichiro YOSHII ,  Koichiro SHINDO ,  Kazushige KAWASAKI ,  Tomoya SANUKI

IPC分类号： H01L27/11573 ,  H01L27/11568 ,  H01L27/11582 ,  H01L21/18 ,  H01L21/768 ,  H01L27/11575 ,  H01L25/065 ,  H01L25/18

摘要： According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US10892270B2

公开(公告)日：2021-01-12

申请号：US16508577

申请日：2019-07-11

申请人： Toshiba Memory Corporation

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L27/11573 ,  H01L27/11582 ,  H01L25/18 ,  H01L27/11568 ,  H01L21/768 ,  H01L21/18 ,  H01L23/00

摘要： According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US20200381283A1

公开(公告)日：2020-12-03

申请号：US16429145

申请日：2019-06-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Chang-Chen Tsao

IPC分类号： H01L21/683 ,  H01L21/68 ,  H01L21/687 ,  H01L21/18

摘要： In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.

公开(公告)号：US10833215B2

公开(公告)日：2020-11-10

申请号：US15263818

申请日：2016-09-13

申请人： AZUR SPACE Solar Power GmbH

发明人： Wolfgang Guter ,  Matthias Meusel ,  Frank Dimroth ,  Lars Ebel ,  Rene Kellenbenz

IPC分类号： H01L31/0687 ,  H01L21/18 ,  H01L31/054 ,  H01L31/028 ,  H01L31/0304

摘要： A multi-junction solar cell having a first subcell made of an InGaAs compound. The first subcell has a first lattice constant and A second subcell has a second lattice constant. The first lattice constant is at least 0.008 Å greater than the second lattice constant. A metamorphic buffer is formed between the first subcell and the second subcell and has a sequence of at least three layers and a lattice constant increases from layer to layer in the sequence in the direction toward the first subcell. The lattice constants of the layers of the buffer are greater than the second lattice constant, and a layer of the metamorphic buffer has a third lattice constant that is greater than the first lattice constant. A number N of compensation layers for compensating the residual stress of the metamorphic buffer is formed between the metamorphic buffer and the first subcell.

公开(公告)号：US10825678B2

公开(公告)日：2020-11-03

申请号：US16582146

申请日：2019-09-25

申请人： DISCO CORPORATION

发明人： Tetsukazu Sugiya

IPC分类号： H01L21/02 ,  H01L21/18 ,  H01L21/304 ,  H01L21/768 ,  H01L21/683

摘要： A wafer processing method includes: a bonding step of bonding a front surface side of a first wafer chamfered at a peripheral edge portion thereof to a front surface side of a second wafer; a grinding step of holding a back surface side of the second wafer by a chuck table and grinding a back surface of the first wafer to thin the first wafer to a finished thickness, after the bonding step; and a modified layer forming step of applying along a boundary between a device region and a peripheral surplus region of the first wafer a laser beam of such a wavelength as to be transmitted through the first wafer to form an annular modified layer inside the first wafer in the vicinity of the front surface of the first wafer, before the grinding step.