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公开(公告)号：US11211362B2
公开(公告)日：2021-12-28
申请号：US16824908
申请日：2020-03-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Xin-Hua Huang , Chung-Yi Yu , Yeong-Jyh Lin , Rei-Lin Chu
IPC: H01L25/065 , H01L23/00 , H01L23/528 , H01L27/01 , H01L23/48 , H01L21/768 , H01L25/00
Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.
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公开(公告)号：US20210335713A1
公开(公告)日：2021-10-28
申请号：US17012490
申请日：2020-09-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Xin-Hua Huang , Chung-Yi Yu , Kuei-Ming Chen
IPC: H01L23/538 , H01L21/768 , H01L23/00 , H01L23/48 , H01L29/778
Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
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公开(公告)号：US11031369B2
公开(公告)日：2021-06-08
申请号：US16654377
申请日：2019-10-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Xin-Hua Huang , Kuan-Liang Liu , Kuo Liang Lu , Ping-Yin Liu
IPC: B23K37/04 , H01L23/00 , H01L21/683 , H01L21/67 , H01L21/20 , H01L21/762 , B23K101/40
Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.
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公开(公告)号：US20190096848A1
公开(公告)日：2019-03-28
申请号：US15935309
申请日：2018-03-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Xin-Hua Huang , Kuan-Liang Liu , Kuo Liang Lu , Ping-Yin Liu
Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.
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公开(公告)号：US11742321B2
公开(公告)日：2023-08-29
申请号：US17319558
申请日：2021-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Xin-Hua Huang , Kuan-Liang Liu , Kuo Liang Lu , Ping-Yin Liu
IPC: B23K37/00 , H01L23/00 , B23K37/04 , H01L21/683 , H01L21/67 , H01L21/20 , H01L21/762 , B23K101/40
CPC classification number: H01L24/94 , B23K37/04 , B23K37/0408 , H01L21/2007 , H01L21/67092 , H01L21/6831 , H01L21/6838 , H01L21/76251 , H01L24/75 , H01L24/83 , B23K2101/40 , H01L2224/753 , H01L2224/759 , H01L2224/75704 , H01L2224/75724 , H01L2224/75744 , H01L2224/83209 , H01L2224/83894 , H01L2224/83908 , H01L2924/1203 , H01L2924/12043 , H01L2924/1304 , H01L2924/1434 , H01L2924/1461 , H01L2924/00012 , H01L2924/12043 , H01L2924/00012 , H01L2924/1434 , H01L2924/00012 , H01L2924/1461 , H01L2924/00012
Abstract: The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.
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Patent Agency Ranking
公开(公告)号：US11721637B2
公开(公告)日：2023-08-08
申请号：US16884437
申请日：2020-05-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Xin-Hua Huang , Ping-Yin Liu
IPC: H01L23/544 , H01L23/00 , B23Q17/22 , H01L21/18 , H01L21/68
CPC classification number: H01L23/544 , H01L24/83 , B23Q17/22 , H01L21/187 , H01L21/681 , H01L2223/54426 , H01L2224/8313
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.
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公开(公告)号：US11222849B2
公开(公告)日：2022-01-11
申请号：US17012490
申请日：2020-09-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Xin-Hua Huang , Chung-Yi Yu , Kuei-Ming Chen
IPC: H01L23/538 , H01L23/48 , H01L29/778 , H01L21/768 , H01L23/00
Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
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公开(公告)号：US20210273167A1
公开(公告)日：2021-09-02
申请号：US16806064
申请日：2020-03-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ping-Yin Liu , Chia-Shiung Tsai , Xin-Hua Huang , Yu-Hsing Chang , Yeong-Jyh Lin
IPC: H01L51/00 , H01L51/50 , H01L51/56 , C23C16/458 , C23C16/04
Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.
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公开(公告)号：US20200064730A1
公开(公告)日：2020-02-27
申请号：US16666679
申请日：2019-10-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ping-Yin Liu , Chang-Ming Wu , Chia-Shiung Tsai , Xin-Hua Huang
Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.
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公开(公告)号：US10509312B2
公开(公告)日：2019-12-17
申请号：US16013163
申请日：2018-06-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ping-Yin Liu , Chang-Ming Wu , Chia-Shiung Tsai , Xin-Hua Huang
Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.
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