METHOD AND DEVICE FOR CHARACTERIZING OR MEASURING A CAPACITANCE
    301.
    发明申请
    METHOD AND DEVICE FOR CHARACTERIZING OR MEASURING A CAPACITANCE 有权
    用于表征或测量电容的方法和装置

    公开(公告)号:US20130057298A1

    公开(公告)日:2013-03-07

    申请号:US13669732

    申请日:2012-11-06

    CPC classification number: G01R27/2605 G06F3/0416 G06F3/044

    Abstract: The disclosure relates to a method for characterizing or measuring a capacitance, comprising: linking the capacitance to a first mid-point of a first capacitive divider bridge, applying to the divider bridge a bias voltage, maintaining the voltage of the first mid-point near a reference voltage, discharging a second mid-point of a second divider bridge in parallel with the first by means of a constant current, and measuring the time for a voltage of the second mid-point to become equal to the voltage of the first mid-point. The disclosure may be applied in particular to the control of a touch screen display.

    Abstract translation: 本发明涉及一种用于表征或测量电容的方法,包括:将电容连接到第一电容分压器桥的第一中点,将分压电桥施加偏置电压,将第一中点的电压保持在接近 参考电压,通过恒定电流将与第一分压器并联的第二分压电桥的第二中点放电,并且测量第二中点的电压的时间变得等于第一中间电压的电压 -点。 本公开可以特别地应用于触摸屏显示器的控制。

    Integrated circuit comprising at least one bipolar transistor and a corresponding method of production

    公开(公告)号:US12289884B2

    公开(公告)日:2025-04-29

    申请号:US17747540

    申请日:2022-05-18

    Abstract: A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.

    Electronic device including an electronic module and a compensation circuit

    公开(公告)号:US12282589B2

    公开(公告)日:2025-04-22

    申请号:US18167521

    申请日:2023-02-10

    Inventor: Nicolas Demange

    Abstract: An electronic device includes a power supply terminal, a voltage regulator connected to the power supply terminal, an electronic module connected to the voltage regulator, and a compensation circuit configured to receive an auxiliary current generated by the voltage regulator and being equal to a first fraction of the electronic module current. The compensation circuit includes a current source configured to supply a source current to a cold point, and a compensation stage connected to the power supply terminal and being traversed by an intermediate current equal to a difference between the source current and the auxiliary current and by a complementary current equal to the intermediate current multiplied by an inverse multiplication factor of the first fraction.

    Phase-change memory
    306.
    发明授权

    公开(公告)号:US12262649B2

    公开(公告)日:2025-03-25

    申请号:US17508754

    申请日:2021-10-22

    Inventor: Philippe Boivin

    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

    Protection of a cryptographic operation

    公开(公告)号:US12250303B2

    公开(公告)日:2025-03-11

    申请号:US17820843

    申请日:2022-08-18

    Inventor: Guilhem Assael

    Abstract: The present disclosure relates to a cryptographic method comprising: multiplying a point belonging to a mathematical set with a group structure by a scalar by performing: the division of a scalar into a plurality of groups formed of a same number w of digits, w being greater than or equal to 2; and the execution, by a cryptographic circuit and for each group of digits, of a sequence of operations on point, the sequence of operations being identical for each group of digits, at least one of the operations executed for each of the groups of digits being a dummy operation.

    METHOD FOR PROTECTING DATA STORED IN A MEMORY, AND CORRESPONDING INTEGRATED CIRCUIT

    公开(公告)号:US20250015016A1

    公开(公告)日:2025-01-09

    申请号:US18887429

    申请日:2024-09-17

    Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

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