公开(公告)号：US20200098524A1

公开(公告)日：2020-03-26

申请号：US16571738

申请日：2019-09-16

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed Boufnichel

IPC: H01G4/30 ,  H01G4/224

Abstract: A vertical capacitor includes a stack of layers conformally covering walls of a first material. The walls extend from a substrate made of a second material different from the first material.

公开(公告)号：US10541089B2

公开(公告)日：2020-01-21

申请号：US15862752

申请日：2018-01-05

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain Charley

IPC: H01G7/06 ,  G05F5/00 ,  H03H5/12 ,  H03H7/01 ,  G01R15/16 ,  H04B1/04

Abstract: A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

公开(公告)号：US20190356136A1

公开(公告)日：2019-11-21

申请号：US16410446

申请日：2019-05-13

Applicant: STMicroelectronics (Tours) SAS

Inventor： Emmanuel Bailly

IPC: H02J7/00 ,  G01R19/165 ,  H01M10/0562 ,  H01M10/0525

Abstract: A method and system of recharging an electric battery, include an alternation of phases of recharge at a constant current and of phases of recharge at constant voltage.

公开(公告)号：US10453835B2

公开(公告)日：2019-10-22

申请号：US16055635

申请日：2018-08-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/66 ,  H01L21/332 ,  H01L27/02 ,  H01L29/74 ,  H01L29/747 ,  H01L29/87 ,  H01L29/417 ,  H01L29/423

Abstract: A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

公开(公告)号：US20190245248A1

公开(公告)日：2019-08-08

申请号：US16268210

申请日：2019-02-05

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Franck FERREIRA GOMES ,  Delphine GUY-BOUYSSOU

IPC: H01M10/0585 ,  H01M10/0562 ,  H01M4/525 ,  H01M2/02 ,  H01M4/66 ,  H01M4/38 ,  H01M4/46

CPC classification number: H01M10/0585 ,  H01M2/0267 ,  H01M4/38 ,  H01M4/386 ,  H01M4/387 ,  H01M4/463 ,  H01M4/525 ,  H01M4/661 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/0562 ,  H01M10/446 ,  H01M2300/0068

Abstract: The disclosure concerns a lithium battery comprising, in order, a support, a copper electrode and, in contact with the copper electrode, a layer of a material capable of forming an alloy with lithium. The disclosure further concerns a manufacturing method and a method of putting into service such a battery.

公开(公告)号：US20190214476A1

公开(公告)日：2019-07-11

申请号：US16230137

申请日：2018-12-21

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Samuel MENARD

IPC: H01L29/47 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74 ,  H01L29/747

CPC classification number: H01L29/47 ,  H01L29/456 ,  H01L29/73 ,  H01L29/7308 ,  H01L29/732 ,  H01L29/74 ,  H01L29/747

Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

公开(公告)号：US10298143B2

公开(公告)日：2019-05-21

申请号：US15877854

申请日：2018-01-23

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Ghafour Benabdelaziz ,  Laurent Gonthier

IPC: H02M1/08 ,  H02M1/32 ,  H02M1/36 ,  H02M1/42 ,  H02M7/06 ,  H02M7/162

Abstract: A rectifying circuit including: between a first terminal of application of an AC voltage and a first rectified voltage delivery terminal, at least one first diode; and between a second terminal of application of the AC voltage and a second rectified voltage delivery terminal, at least one first anode-gate thyristor, the anode of the first thyristor being connected to the second rectified voltage delivery terminal; and at least one first stage for controlling the first thyristor, including: a first transistor coupling the thyristor gate to a terminal of delivery of a potential which is negative with respect to the potential of the second rectified voltage delivery terminal; and a second transistor connecting a control terminal of the first transistor to a terminal for delivering a potential which is positive with respect to the potential of the second rectified voltage delivery terminal, the anode of the first thyristor being connected to the common potential of voltages defined by said positive and negative potentials.

公开(公告)号：US10276308B2

公开(公告)日：2019-04-30

申请号：US15812438

申请日：2017-11-14

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain Charley

IPC: H01G7/00 ,  H03H11/48

Abstract: A circuit for controlling a capacitor having a capacitance adjustable by biasing, including an amplifier for delivering a D.C. bias voltage, having a feedback slowed down by a resistive and capacitive cell.

公开(公告)号：US10236480B2

公开(公告)日：2019-03-19

申请号：US16031099

申请日：2018-07-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/04 ,  H01M2/06 ,  H01M2/20 ,  H01M10/04 ,  H01M2/30 ,  H01M2/10

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

公开(公告)号：US10211326B2

公开(公告)日：2019-02-19

申请号：US15362919

申请日：2016-11-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/747 ,  H01L29/66 ,  H01L29/40

Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.