公开(公告)号：US11562974B2

公开(公告)日：2023-01-24

申请号：US17160332

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/00

Abstract: A hybrid bonding structure includes a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive layer. A first barrier surrounds the first conductive layer. A first air gap surrounds and contacts the first barrier. A first dielectric layer surrounds and contacts the first air gap. The second conductive structure includes a second conductive layer. A second barrier contacts the second conductive layer. A second dielectric layer surrounds the second barrier. The second conductive layer bonds to the first conductive layer. The first dielectric layer bonds to the second dielectric layer.

公开(公告)号：US20230020783A1

公开(公告)日：2023-01-19

申请号：US17406084

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wei Tsou ,  Chang-Ting Lo

IPC: G01R31/3185 ,  G01R31/319

Abstract: A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

公开(公告)号：US20230018710A1

公开(公告)日：2023-01-19

申请号：US17386554

申请日：2021-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Ren Huang ,  Chen-Hsiao Wang ,  Kai-Kuang Ho

IPC: H01L21/78 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/66

Abstract: A wafer with a test structure includes a wafer with a front side and a back side. A first die, a second die, a third die and a scribe line are disposed on the wafer. The scribe line is positioned between the dice. The first die includes a first dielectric layer and a first metal connection disposed within and on the first dielectric layer. A test structure and a dielectric layer are disposed on the scribe line, wherein the test structure is on the dielectric layer. Two first trenches are respectively disposed between the first dielectric layer and the dielectric layer and disposed at one side of the dielectric layer. Two second trenches penetrate the wafer, and each of the two second trenches respectively connects to a corresponding one of the two first trenches. A grinding tape covers the front side of the wafer and contacts the test structure.

公开(公告)号：US20230018513A1

公开(公告)日：2023-01-19

申请号：US17952327

申请日：2022-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H01L27/22 ,  H01L43/02

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

公开(公告)号：US20230015480A1

公开(公告)日：2023-01-19

申请号：US17391067

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Chien-Liang Wu ,  Te-Wei Yeh

IPC: H01L27/112

Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

公开(公告)号：US20230014945A1

公开(公告)日：2023-01-19

申请号：US17945122

申请日：2022-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/10

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

公开(公告)号：US20230013358A1

公开(公告)日：2023-01-19

申请号：US17951058

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.

公开(公告)号：US11557654B2

公开(公告)日：2023-01-17

申请号：US17511586

申请日：2021-10-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

公开(公告)号：US11551955B2

公开(公告)日：2023-01-10

申请号：US16831739

申请日：2020-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Che Lai ,  Hua-Wei Peng ,  Chia-He Cheng ,  Ming-Tso Chen ,  Chao-Chi Lu ,  Hsin-Hsu Lin ,  Kuo-Tsai Lo ,  Kao-Hua Wu ,  Huan-Hsin Yeh

IPC: H01L21/67 ,  G05B19/418 ,  G06T7/00

Abstract: A substrate processing apparatus includes a process station for processing a substrate; a cassette station integrated with the process station; a substrate carriage equipped for transferring the substrate between said process station and the cassette station through a passage located at an interface between the process station and said cassette station; and a substrate scanner equipped at said interface between the process station and the cassette station for capturing surface image data during transportation of the substrate that passes through the passage.

公开(公告)号：US20230005833A1

公开(公告)日：2023-01-05

申请号：US17943215

申请日：2022-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L27/01

Abstract: A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.