System for controlling linear axis of a MEMS mirror

    公开(公告)号:US11368656B2

    公开(公告)日:2022-06-21

    申请号:US17356162

    申请日:2021-06-23

    Abstract: A device has memory and processing circuitry coupled to the memory. The processing circuitry generates a resonant axis drive signal to drive a Micro Electro Mechanical System (MEMS) mirror system at a resonance frequency, and generates a linear axis drive signal to drive the MEMS mirror system at a linear frequency corresponding to a video frame rate. Generating the linear axis drive signal includes generating, using interpolation, a current set of shape values based on a stored set of shape values and an indication of the video frame rate. The linear axis drive signal is generated using the current set of shape values.

    COMPACT LINE SCAN MEMS TIME OF FLIGHT SYSTEM WITH ACTUATED LENS

    公开(公告)号:US20220187591A1

    公开(公告)日:2022-06-16

    申请号:US17533890

    申请日:2021-11-23

    Abstract: Disclosed herein is an optical module including a substrate, with an optical detector, laser emitter, and support structure being carried by the substrate. An optical layer includes a fixed portion carried by the support structure, a movable portion affixed between opposite sides of the fixed portion by a spring structure, and a lens system carried by the movable portion. The movable portion has at least one opening defined therein across which the lens system extends, with at least one supporting portion extending across the at least one opening to support the lens system. The optical layer further includes a MEMS actuator for in-plane movement of the movable portion with respect to the fixed portion.

    HARDWARE ACCELERATOR DEVICE, CORRESPONDING SYSTEM AND METHOD OF OPERATION

    公开(公告)号:US20220180959A1

    公开(公告)日:2022-06-09

    申请号:US17453811

    申请日:2021-11-05

    Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

    SWITCHING CONVERTER
    318.
    发明申请

    公开(公告)号:US20220166321A1

    公开(公告)日:2022-05-26

    申请号:US17532867

    申请日:2021-11-22

    Abstract: In an embodiment, a switching converter includes: a switching stage configured to receive a direct current input voltage, receive a driving signal for driving the switching stage, and provide a direct current output voltage according to the input voltage and the driving signal; a driving stage configured to provide the driving signal to the switching stage; a current sensing circuit configure to sense an output current provided by the switching stage; and a voltage generation circuit configured to generate at least one supply voltage for powering the driving stage, and adjust the at least one supply voltage according to the output current.

    SWITCHING CONVERTER
    319.
    发明申请

    公开(公告)号:US20220166320A1

    公开(公告)日:2022-05-26

    申请号:US17532833

    申请日:2021-11-22

    Abstract: In an embodiment, a switching converter includes: a switching stage including first and second switching devices for receiving an input voltage and for providing an output voltage; a driving stage including first and second driving devices for driving the first and second switching devices, respectively; a current sensing arrangement for sensing an output current provided by the switching stage; a voltage generation arrangement configured to generate a supply voltage for powering the driving stage, the voltage generation arrangement being configured to adjust the supply voltage according to the sensed output current; and a charge recovery stage configured to store a first electric charge being lost from the first driving device during driving of the first switching device and to release at least partially the stored first electric charge to the second driving device during driving of the second switching device.

    Detection circuit, corresponding device and method

    公开(公告)号:US11342885B2

    公开(公告)日:2022-05-24

    申请号:US16698060

    申请日:2019-11-27

    Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.

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