公开(公告)号：US20060244042A1

公开(公告)日：2006-11-02

申请号：US11413640

申请日：2006-04-28

Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.

Abstract translation: 在分闸式非易失存储器件及其制造方法中， 辅助层图案设置在半导体衬底的源极区域上。 由于源区域由于存在辅助层图案而垂直延伸，因此可以增加浮置栅极与源区域和辅助层图案重叠的区域的面积。 因此，形成在源极和浮置栅极之间的电容器的电容增加，使得非易失性存储器件可以在低电压电平下执行编程/擦除操作。

公开(公告)号：US20060199359A1

公开(公告)日：2006-09-07

申请号：US11415466

申请日：2006-05-01

Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/792

Abstract: In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In addition, the local-length nitride layer is self-aligned, which prevents nitride misalignment, and therefore leads to reduced threshold voltage variation among the devices.

Abstract translation: 在本地长度的氮化物SONOS器件及其形成方法中，提供局部长度的氮化物浮栅结构，用于减轻或防止氮化物浮栅中的横向电子迁移。 该结构包括薄栅极氧化物，其导致具有较低阈值电压的器件。 此外，局部长度的氮化物层是自对准的，这防止氮化物不对准，并且因此导致器件之间的阈值电压变化降低。

公开(公告)号：US07097943B2

公开(公告)日：2006-08-29

申请号：US10275384

申请日：2001-01-31

Applicant: Byung-Won Cho ,  Won-Il Cho ,  Hyung-Sun Kim ,  Un-Sek Kim ,  Hee-Woo Rhee ,  Yong-Tae Kim ,  Min-Kyu Song

Inventor： Byung-Won Cho ,  Won-Il Cho ,  Hyung-Sun Kim ,  Un-Sek Kim ,  Hee-Woo Rhee ,  Yong-Tae Kim ,  Min-Kyu Song

IPC: H01M6/18

CPC classification number: H01M10/0565 ,  H01M6/168 ,  H01M10/052 ,  H01M2300/0082 ,  H01M2300/0088

Abstract: The present invention relates to a UV-cured multi-component polymer blend electrolyte, lithium secondary battery and their fabrication method, wherein the UV-cured multi-component polymer blend electrolyte, comprises: A) function-I polymer obtained by curing ethyleneglycoldi-(meth)acrylate oligomer of formula 1 by UV irradiation, CH2═CR1COO(CH2CH2O)nCOCR2═CH2 (1) wherein, R1 and R2 are independently a hydrogen or methyl group, and n is an integer of 3-20; B) function-II polymer selected from the group consisting of PAN-based polymer, PMMA-based polymer and mixtures thereof; C) function-III polymer selected from the group consisting of PVdF-based polymer, PVC-based polymer and mixtures thereof; and D) organic electrolyte solution in which lithium salt is dissolved in a solvent.

Abstract translation: 本发明涉及一种UV固化多组分聚合物共混电解质，锂二次电池及其制造方法，其中UV固化的多组分聚合物共混电解质包括：A）通过将乙二醇（ 甲基）丙烯酸酯低聚物，通过UV照射，CH 2 CO 2（CH 2 CH 2 CH 2） （1）其中，R 1和R 2各自独立地为氢， / SUP>独立地为氢或甲基，n为3-20的整数; B）选自PAN基聚合物，PMMA基聚合物及其混合物的官能团II聚合物; C）选自PVdF基聚合物，基于PVC的聚合物及其混合物的功能III聚合物; 和D）其中锂盐溶解在溶剂中的有机电解质溶液。

公开(公告)号：US20060170034A1

公开(公告)日：2006-08-03

申请号：US11339741

申请日：2006-01-25

Applicant: Sung-Woo Park ,  Sung-Taeg Kang ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Ji-Hoon Park

Inventor： Sung-Woo Park ,  Sung-Taeg Kang ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Ji-Hoon Park

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/792

Abstract: Provided are a non-volatile memory device having an improved electric characteristic and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a substrate having a sloped portion formed therein, a first gate electrode pattern having a stacked structure in which an electric charge tunneling layer pattern, an electric charge trapping layer pattern, an electric charge shielding layer pattern, and a storage gate electrode pattern are conformably stacked on the sloped portion, a gate insulating layer pattern extending from a side of the first gate electrode pattern to the substrate, a second gate electrode pattern formed on the gate insulating layer pattern, a first junction region arranged at a side wall of the first gate electrode pattern, which does not face the second gate electrode pattern, and formed in the substrate, and a second junction region arranged at a side wall of the second gate electrode pattern, which does not face the first gate electrode pattern, and formed in the substrate.

Abstract translation: 提供了具有改进的电特性的非易失性存储器件和制造非易失性存储器件的方法，其中非易失性存储器件包括其中形成有倾斜部分的衬底，第一栅电极图案具有堆叠 其中电荷隧道层图案，电荷捕获层图案，电荷屏蔽层图案和存储栅极电极图案顺应地堆叠在倾斜部分上的结构，从第一部分的侧面延伸的栅极绝缘层图案 栅电极图案到基板，形成在栅极绝缘层图案上的第二栅极电极图案，布置在第一栅电极图案的侧壁处的第一接合区域，其不面向第二栅电极图案，并形成在第 衬底和布置在第二栅电极图案的侧壁处的第二接合区域，其不面向顶部 t栅电极图案，并形成在基板中。

公开(公告)号：US20050142667A1

公开(公告)日：2005-06-30

申请号：US10922949

申请日：2004-08-23

Applicant: Yong-Tae Kim ,  Seong-Il Kim ,  Chun-Keun Kim ,  Sun-Il Shim

Inventor： Yong-Tae Kim ,  Seong-Il Kim ,  Chun-Keun Kim ,  Sun-Il Shim

IPC: H01L21/3065 ,  H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/6684 ,  H01L21/2652 ,  H01L21/28291 ,  H01L29/66575

Abstract: A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.

Abstract translation: 公开了使用具有高蚀刻选择性的缓冲层的自对准铁电栅极晶体管的制造方法。 在硅衬底和铁电体层之间形成具有高蚀刻选择性的缓冲层的堆叠结构，并且对形成源极和漏极的部分进行蚀刻，然后在缓冲层处停止， 自对准的铁电栅极晶体管，而不损坏硅薄膜，从而可以提高芯片的集成度。

公开(公告)号：US06621685B1

公开(公告)日：2003-09-16

申请号：US10339398

申请日：2003-01-10

Applicant: Byung-Won Cho ,  Hee-Woo Rhee ,  Won-Il Cho ,  Hyun-Joong Kim ,  Chun-Mo Yang ,  Yong-Tae Kim

Inventor： Byung-Won Cho ,  Hee-Woo Rhee ,  Won-Il Cho ,  Hyun-Joong Kim ,  Chun-Mo Yang ,  Yong-Tae Kim

IPC: H01G900

CPC classification number: H01G9/038 ,  H01G11/56 ,  Y02E60/13 ,  Y02T10/7022

Abstract: Disclosed is an electric double-layered capacitor fabricated by inserting a UV-curing gel type polymer electrolyte having excellent characteristics of ion conductivity, adhesion to electrode, compatibility with an organic solvent electrolyte, mechanical stability, permeability, and applicability to process, between electrodes. Accordingly, the present invention increases its storage capacitance, reduces self-discharge of electricity, and decreases inner cell resistance.

Abstract translation: 公开了一种电双层电容器，其通过在电极之间插入具有优异的离子传导性，电极粘附性，与有机溶剂电解质的相容性，机械稳定性，渗透性和加工性的紫外线固化型凝胶型聚合物电解质。 因此，本发明增加其存储电容，减少电力的自放电，并降低内电池电阻。

公开(公告)号：US06392921B1

公开(公告)日：2002-05-21

申请号：US09900184

申请日：2001-07-09

Applicant: Yong Tae Kim ,  Chun Keun Kim ,  Seong Il Kim ,  Sun Il Shim

Inventor： Yong Tae Kim ,  Chun Keun Kim ,  Seong Il Kim ,  Sun Il Shim

IPC: G11C1100

CPC classification number: G11C11/22

Abstract: The driving circuit for an NDRO-FRAM includes several NDRO-FRAM (Non Destructive Non Volatile Ferroelectric Random Access Memory) cells each having a drain, a bulk, a source and a gate and arranged as a matrix. A plurality of reading word lines are separately connected to each drain of the NDRO-FRAM cells arranged in columns, and a plurality of writing word lines are separately connected to each bulk of the NDRO-FRM cells arranged in columns. Several data level transmission circuits for transmitting a data level of the NDRO-FRAM cells are also included, which are connected to a plurality of data level transmission circuits. Accordingly, the present invention is capable of reading and writing of data on the NDRO-FRAM cells.

Abstract translation: NDRO-FRAM的驱动电路包括几个NDRO-FRAM（非破坏性非易失性铁电随机存取存储器）单元，每个单元具有漏极，体积，源极和栅极并且被布置为矩阵。 多个读取字线分别连接到排列成列的NDRO-FRAM单元的每个漏极，并且多个写入字线分别连接到以列布置的NDRO-FRM单元的大部分。 还包括用于发送NDRO-FRAM单元的数据电平的几个数据电平传输电路，其连接到多个数据电平传输电路。 因此，本发明能够读取和写入NDRO-FRAM单元上的数据。

公开(公告)号：US06220045B1

公开(公告)日：2001-04-24

申请号：US09448287

申请日：1999-11-24

Applicant: Yong Tae Kim

Inventor： Yong Tae Kim

IPC: F25B4902

CPC classification number: F25B49/025 ,  F25B2600/021 ,  Y02B30/741

Abstract: The present invention relates to an apparatus and method for controlling the operating speed of a compressor of an inverter refrigerator. In an apparatus or method embodying the present invention, one knows the operating speeds which will cause the compressor to experience resonant vibrations. When it is necessary to change from a first operating frequency to a second operating frequency, and a resonant frequency band is located between the first and second frequencies, the controller will accelerate the rate of change of the operating frequency as it passes through the resonant frequency band to minimize the amount of time that the compressor is operating within the resonant frequency band.

Abstract translation: 本发明涉及一种用于控制逆变器冰箱的压缩机的运行速度的装置和方法。 在体现本发明的装置或方法中，人们知道将导致压缩机经历共振振动的操作速度。 当需要从第一工作频率改变到第二工作频率，并且谐振频带位于第一和第二频率之间时，控制器将在其通过谐振频率时加速工作频率的变化率 以最小化压缩机在谐振频带内操作的时间量。