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    CHARACTERIZATION OF IN-CHIP ERROR CORRECTION CIRCUITS AND RELATED SEMICONDUCTOR MEMORY DEVICES/MEMORY SYSTEMS
    1.
    发明申请
    CHARACTERIZATION OF IN-CHIP ERROR CORRECTION CIRCUITS AND RELATED SEMICONDUCTOR MEMORY DEVICES/MEMORY SYSTEMS 审中-公开
    芯片内错误校正电路和相关半导体存储器件/存储器系统的特征

    公开(公告)号：US20160378597A1

    公开(公告)日：2016-12-29

    申请号：US15194102

    申请日：2016-06-27

    申请人： Hoi-Ju Chung ,  Sang-Uhn CHA ,  Hyun-Joong KIM

    发明人： Hoi-Ju Chung ,  Sang-Uhn CHA ,  Hyun-Joong KIM

    IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C29/52

    CPC分类号： H04L1/24 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411

    摘要： A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

    摘要翻译： 操作半导体存储器件的方法可以包括从存储器控制器接收包括在半导体存储器件中的纠错码（ECC）引擎的数据，该数据包括至少一个预定误差。 可以在ECC引擎处接收预定奇偶校验，其中预定奇偶校验被配置为对应于数据而没有至少一个预定错误。 可以确定ECC引擎使用包括至少一个预定错误和预定奇偶校验的数据来校正数据中的多个错误。

    Die packages and systems having the die packages
    4.
    发明授权
    Die packages and systems having the die packages 有权
    具有管芯封装的管芯封装和系统

    公开(公告)号：US08710655B2

    公开(公告)日：2014-04-29

    申请号：US13546517

    申请日：2012-07-11

    申请人： Hyun-Joong Kim ,  Jang Seok Choi ,  Chul-Hwan Choo

    发明人： Hyun-Joong Kim ,  Jang Seok Choi ,  Chul-Hwan Choo

    IPC分类号： H01L23/48 ,  H05K7/20

    CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1301 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.

    摘要翻译： 管芯封装可以包括封装衬底; 中介者 和/或连接在封装衬底和插入件之间的至少一个第一管芯。 管芯封装还可包括安装在插入件和/或处理器上的至少一个第二管芯。 系统可以包括安装在系统板上的系统板和/或管芯封装。 管芯封装可以包括封装衬底; 中介者 和/或连接在封装衬底和插入件之间的至少一个第一管芯。 系统还可以包括安装在插入器和/或处理器上的至少一个第二裸片。 处理器可以控制至少一个第一管芯和/或至少一个第二管芯的数据处理操作。

    METHOD FOR WELDING TIP OF ELECTRODE IN SPARK PLUG
    5.
    发明申请
    METHOD FOR WELDING TIP OF ELECTRODE IN SPARK PLUG 有权
    火花塞电极焊接方法

    公开(公告)号：US20100258541A1

    公开(公告)日：2010-10-14

    申请号：US12741511

    申请日：2008-04-02

    申请人： Dae Yeol Ohm ,  Seok Ki Song ,  Hyun Joong Kim ,  Byung Heon Shin ,  Young Tae Yoo

    发明人： Dae Yeol Ohm ,  Seok Ki Song ,  Hyun Joong Kim ,  Byung Heon Shin ,  Young Tae Yoo

    IPC分类号： B23K26/00

    CPC分类号： B23K26/32 ,  B23K26/0622 ,  B23K26/28 ,  B23K2101/006 ,  B23K2101/36 ,  B23K2103/08 ,  B23K2103/18 ,  B23K2103/26 ,  H01T21/02

    摘要： A method of welding a noble metal tip of a spark plug to an electrode is provided. In the method of welding, in a waveform of a power of a laser beam according to a time of the laser welding, a power of a central portion thereof is smaller than those of both end portions thereof. In addition, the waveform of the power of the laser beam according to a time of the laser welding is a trapezoidal waveform which includes: a rising portion in which the power of the laser beam is gradually increased; a power maintaining portion in which the power of the laser beam after the rising portion is maintained uniform; and a falling portion in which the power of the laser beam after the power maintaining portion is gradually decreased. In addition, the waveform of the power of the laser beam according to a time of the laser welding is a triangular waveform which includes: a rising portion in which the power of the laser beam is gradually increased; and a falling portion in which the power of the laser beam after the rising portion is gradually decreased. Accordingly, it is possible to securely attach the electrode tip to a central electrode or a ground electrode.

    摘要翻译： 提供了将火花塞的贵金属端头焊接到电极的方法。 在焊接方法中，根据激光焊接时的激光束的功率波形，其中心部分的功率小于其两端部的功率。 此外，根据激光焊接时间的激光束的功率波形是梯形波形，其包括：激光束的功率逐渐增加的上升部分; 功率保持部，其中激光束在上升部分之后的功率保持均匀; 以及其中在功率保持部分之后的激光束的功率逐渐减小的下降部分。 此外，根据激光焊接的时间的激光束的功率的波形是三角波形，其包括：激光束的功率逐渐增加的上升部分; 以及在上升部分之后激光束的功率逐渐减小的下降部分。 因此，可以将电极头牢固地固定到中心电极或接地电极。

    Memory controller, memory system including the memory controller, and operating method performed by the memory controller
    7.
    发明申请
    Memory controller, memory system including the memory controller, and operating method performed by the memory controller 有权
    存储器控制器，包括存储器控制器的存储器系统和由存储器控制器执行的操作方法

    公开(公告)号：US20140157045A1

    公开(公告)日：2014-06-05

    申请号：US14096824

    申请日：2013-12-04

    申请人： Hyun-joong Kim ,  Tae-young Oh

    发明人： Hyun-joong Kim ,  Tae-young Oh

    IPC分类号： G06F11/07

    CPC分类号： G11C29/76 ,  G06F11/073

    摘要： Provided are a memory controller, a memory system including the memory controller, and an operating method performed by the memory controller. The operating method includes operations of queuing a first command in a first queue, detecting a fail of a first address that corresponds to the first command, when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address, and outputting the second command and the second address from the first queue.

    摘要翻译： 提供了存储器控制器，包括存储器控制器的存储器系统和由存储器控制器执行的操作方法。 操作方法包括在第一队列中排队第一命令，检测到与第一命令相对应的第一地址的失败的操作，当第一地址被确定为故障地址时，排队第二地址和第二命令中的第二命令 第一队列，其中通过重新映射第一地址获得第二地址，并且第二命令对应于第二地址，并且从第一队列输出第二命令和第二地址。

    Multi channel semiconductor memory device and semiconductor device including the same
    8.
    发明授权
    Multi channel semiconductor memory device and semiconductor device including the same 有权
    多通道半导体存储器件和包括其的半导体器件

    公开(公告)号：US08717828B2

    公开(公告)日：2014-05-06

    申请号：US13298653

    申请日：2011-11-17

    申请人： Hyun-Joong Kim ,  Dongyang Lee

    发明人： Hyun-Joong Kim ,  Dongyang Lee

    IPC分类号： G11C7/00 ,  G11C7/22

    CPC分类号： G11C5/063 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.

    摘要翻译： 公开了一种半导体存储器件，其包括安装在封装内的多个通道存储器，并且能够最小化或减少硅通孔的数量。 利用半导体存储器件，通过共享总线施加两个或更多个通道上的行命令或行地址。 半导体存储器件能够通过减少硅通孔的数量来减少管芯​​尺寸的开销。 还提供了使用共享总线驱动包括多个存储器的多通道半导体存储器件的方法。

    Temperature sensing circuit of semiconductor device
    10.
    发明授权
    Temperature sensing circuit of semiconductor device 有权
    半导体器件温度检测电路

    公开(公告)号：US08342747B2

    公开(公告)日：2013-01-01

    申请号：US12694624

    申请日：2010-01-27

    申请人： Si-Hong Kim ,  Kwang-Il Park ,  Hyun-Joong Kim

    发明人： Si-Hong Kim ,  Kwang-Il Park ,  Hyun-Joong Kim

    IPC分类号： G01K7/14

    CPC分类号： G01K1/02 ,  G01K7/32 ,  G01K2219/00

    摘要： A temperature sensing circuit of a semiconductor device includes a code signal generator, a comparator, a reference clock generator and a final temperature code signal generator. The code signal generator is configured to output a first count signal having an increase rate that varies according to a change in temperature. The comparator is configured to receive the first count signal and a control signal, compare the first count signal with the control signal and output a comparison signal. The reference clock generator is configured to generate a reference clock having a uniform period regardless of the change in temperature during an activation period of the comparison signal. The final temperature code signal generator is configured to count pulses of the reference clock, generate a second count signal, modify the second count signal using an offset value, and output the modified second count signal as a final temperature code signal.

    摘要翻译： 半导体器件的温度检测电路包括代码信号发生器，比较器，参考时钟发生器和最终温度代码信号发生器。 代码信号发生器被配置为输出具有根据温度变化而变化的增加率的第一计数信号。 比较器被配置为接收第一计数信号和控制信号，将第一计数信号与控制信号进行比较并输出比较信号。 参考时钟发生器被配置为在比较信号的激活周期期间生成具有均匀周期的参考时钟，而不管温度变化。 最终温度代码信号发生器被配置为对参考时钟的脉冲进行计数，产生第二计数信号，使用偏移值修改第二计数信号，并输出修改的第二计数信号作为最终温度代码信号。