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公开(公告)号：US20240128997A1
公开(公告)日：2024-04-18
申请号：US18478615
申请日：2023-09-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Tramoni
CPC classification number: H04B5/0031 , H02J7/00034 , H02J50/23 , H04B5/0081
Abstract: An electronic device includes a power supply, such as a battery, configured to supply a power supply voltage. The device further includes a controllable voltage converter circuit configured to generate a control voltage based on the power supply voltage. A near-field communication device is included that has at least one antenna configured to emit an electromagnetic field having a power that is controllable by the control voltage. The electronic device further includes a temperature measuring device configured to measure a temperature. The controllable voltage converter circuit is configured to modify a value of the control voltage based on the measured temperature.
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公开(公告)号：US11954548B2
公开(公告)日：2024-04-09
申请号：US17520266
申请日：2021-11-05
Inventor： Frederic Gouabau , Olivier Rouy
IPC: G06K19/07 , G06K19/073 , H05B45/10
CPC classification number: G06K19/07354 , H05B45/10
Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.
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323.发明公开公开(公告)号：US20240114324A1
公开(公告)日：2024-04-04
申请号：US18525496
申请日：2023-11-30
Applicant: STMicroelectronics (Rousset) SAS , STMICROELECTRONICS GMBH
Inventor： Thierry Meziache , Pierre Rizzo , Alexandre Charles , Juergen Boehler
CPC classification number: H04W4/80 , G06K7/0008 , G06K7/10237 , G06K7/10247 , H04B5/0031
Abstract: A device, including a main element and a set of at least two auxiliary elements, the main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to the master SWP interface of the NFC element through a controllably switchable SWP link and management circuit configured to control the SWP link switching for selectively activating at once only one slave SWP interface on the SWP link.
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公开(公告)号：US20240103873A1
公开(公告)日：2024-03-28
申请号：US18532946
申请日：2023-12-07
Inventor： Michael PEETERS , Fabrice MARINET
IPC: G06F9/30
CPC classification number: G06F9/30185 , G06F9/30134 , G06F9/30145 , G06F9/30105
Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
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公开(公告)号：US20240097701A1
公开(公告)日：2024-03-21
申请号：US18463844
申请日：2023-09-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Michel Cuenca , Didier Davino
IPC: H03M1/70
CPC classification number: H03M1/70
Abstract: One embodiment provides a digital-to-analog converter that includes an output amplifier configured to be powered with a controllable power supply voltage and a ground reference voltage. The output amplifier is configured to generate an analog output signal having a dynamic range centered on a common-mode voltage. The output amplifier includes a common-mode adaptation circuit configured to position a level of the common-mode voltage at a level located in a middle portion of an interval of voltages located between the power supply voltage and the ground reference voltage, according to an effective level of the power supply voltage.
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Patent Agency Ranking
公开(公告)号：US11935828B2
公开(公告)日：2024-03-19
申请号：US18116672
申请日：2023-03-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak Marzaki
IPC: H01L23/522 , H01L21/762 , H01L27/08 , H01L29/66
CPC classification number: H01L23/5223 , H01L21/76224 , H01L27/0805 , H01L29/66181
Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
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公开(公告)号：US20240089860A1
公开(公告)日：2024-03-14
申请号：US18243175
申请日：2023-09-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre TRAMONI
CPC classification number: H04W52/0274 , H04B1/69 , H04B5/0025
Abstract: A wireless communication device includes a battery, and a platform powered by the battery, with the platform including a processor. The device also includes a voltage regulator powered by the battery, an ultra-wideband communication unit powered by the voltage regulator via the platform when the platform is powered up, and a near-field communication unit powered directly by the battery, and being configured to order the voltage regulator to power the ultra-wideband communication unit when the platform is powered down.
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公开(公告)号：US20240086891A1
公开(公告)日：2024-03-14
申请号：US18242980
申请日：2023-09-06
Inventor： Pierre RIZZO , Laurent TRICHEUR
CPC classification number: G06Q20/3278 , H04B5/0031
Abstract: A first near-field communication device detects the presence of a second near-field communication device located within range. In response to that detection, there is an initiation of a near-field communication between the first and second devices. In case of a failure of the initiation of the near-field communication, instead an initiation of a contactless bank transaction between the first and second devices occurs.
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公开(公告)号：US11928541B2
公开(公告)日：2024-03-12
申请号：US17292149
申请日：2019-10-23
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jose Mangione , Andrei Tudose , Pierre Yves Baudrion , Joran Pantel
IPC: G06K19/077 , G06K19/07 , H01Q7/00 , H04B5/00
CPC classification number: G06K19/07798 , G06K19/0722 , H01Q7/00 , H04B5/0062 , H04B5/0075
Abstract: A closed container includes a detection device for detecting opening of or an attempt to open the container. The detection device includes a contactless passive transponder that is configured to communicate with a reader via an antenna using a carrier signal. An integrated circuit of the transponder includes two input terminals connected to the antenna and two output terminals linked by a first electrically conductive wire having a severable part which is severed in the event of an opening of or an attempted opening of the container. A shorting circuit is configured to short-circuit a first output terminal with a first input terminal in the event of a conductive repair of the severed part which forms an electrical connection between the two output terminals.
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公开(公告)号：US20240074134A1
公开(公告)日：2024-02-29
申请号：US18230952
申请日：2023-08-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Paul DEVOGE , Abderrezak MARZAKI , Franck JULIEN , Alexandre MALHERBE
IPC: H10B10/00 , H01L29/66 , H01L29/788
CPC classification number: H10B10/12 , H01L29/66825 , H01L29/788
Abstract: An integrated circuit includes transistor. That transistor is manufactured using a process including the following steps: forming a first gate region; depositing dielectric layers accumulating on sides of the first gate region to form regions of spacers having a width; etching to remove a part of the deposited dielectric layers accumulated on the sides of the first gate region to reduce the width of the regions of spacers; performing a first implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the transistor; and performing a second implanting of dopants to form first more strongly doped conduction regions of the transistor.
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