公开(公告)号：US10685874B1

公开(公告)日：2020-06-16

申请号：US16220565

申请日：2018-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Lei Sun ,  Lars Liebmann ,  Daniel Chanemougame ,  Guillaume Bouche

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

公开(公告)号：US10665590B2

公开(公告)日：2020-05-26

申请号：US16162373

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  William Taylor ,  Hui Zang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure relates to integrated circuit (IC) structures and their method of manufacture. More particularly, the present disclosure relates to forming a semiconductor device having generally fork-shaped contacts around epitaxial regions to increase surface contact area and improve device performance. The integrated circuit (IC) structure of the present disclosure comprises a plurality of fins disposed on a semiconductor substrate, at least one epitaxial region laterally disposed on selected fins, and a contact material positioned over and surrounding the epitaxial region.

公开(公告)号：US20200161315A1

公开(公告)日：2020-05-21

申请号：US16196060

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Wei Hong ,  Hui Zang ,  David P. Brunco

IPC: H01L27/11

Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.

公开(公告)号：US10651173B1

公开(公告)日：2020-05-12

申请号：US16204506

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Hui Zang ,  Ruilong Xie ,  Haiting Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.

公开(公告)号：US20200119000A1

公开(公告)日：2020-04-16

申请号：US16161294

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Guowei Xu ,  Scott Beasor

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.

公开(公告)号：US20200111713A1

公开(公告)日：2020-04-09

申请号：US16150651

申请日：2018-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Shesh Mani Pandey ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.

公开(公告)号：US10593757B2

公开(公告)日：2020-03-17

申请号：US15961912

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Ruilong Xie ,  Hui Zang ,  Haiting Wang

IPC: H01L29/08 ,  H01L29/78 ,  C30B29/40 ,  H01L29/66 ,  H01L21/02 ,  C30B25/04

Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US20200075715A1

公开(公告)日：2020-03-05

申请号：US16121058

申请日：2018-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal Kamineni ,  Shesh Mani Pandey ,  Hui Zang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768

Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.

公开(公告)号：US20200066588A1

公开(公告)日：2020-02-27

申请号：US16112511

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Haiting Wang

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/66

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.