公开(公告)号：US10403742B2

公开(公告)日：2019-09-03

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US20160111335A1

公开(公告)日：2016-04-21

申请号：US14977387

申请日：2015-12-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： David P. Brunco

IPC: H01L21/8234 ,  H01L29/10 ,  H01L21/266 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/823412 ,  H01L21/0245 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7849

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

公开(公告)号：US08828839B2

公开(公告)日：2014-09-09

申请号：US13753269

申请日：2013-01-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： David P. Brunco ,  Witold Maszara

IPC: H01L21/00 ,  H01L21/762

CPC classification number: H01L21/762 ,  H01L21/0337 ,  H01L21/31144 ,  H01L29/66795 ,  Y10S438/942 ,  Y10S438/947

Abstract: Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces.

Abstract translation: 提供半导体器件结构的制造方法。 在示例性实施例中，制造电隔离FinFET半导体器件的方法包括以下步骤：在包括硅材料的半导体衬底上形成氧化硅层，并在氧化硅层上形成第一硬掩模层。 该方法还包括在第一硬掩模层中形成第一多个空隙空间并在第一多个空隙空间中形成第二硬掩模层的步骤。 此外，该方法包括以下步骤：去除第一硬掩模层的剩余部分，从而在第二硬掩模层中形成第二多个空隙，将第二多个空隙空间延伸到氧化硅层中，并形成 在延伸的第二多个空隙空间中的多个翅片结构。

公开(公告)号：US20180012805A1

公开(公告)日：2018-01-11

申请号：US15699138

申请日：2017-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： David P. Brunco

IPC: H01L21/8234 ,  H01L29/165 ,  H01L29/10 ,  H01L21/762 ,  H01L21/02 ,  H01L21/266 ,  H01L21/265 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/0245 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7849

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

公开(公告)号：US09793168B2

公开(公告)日：2017-10-17

申请号：US14977387

申请日：2015-12-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： David P. Brunco

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L21/266

CPC classification number: H01L21/823412 ,  H01L21/0245 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7849

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

公开(公告)号：US09299809B2

公开(公告)日：2016-03-29

申请号：US13716758

申请日：2012-12-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco

IPC: H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes forming a silicon/germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成硅/锗翅片，其中所述翅片具有第一锗浓度，使绝缘材料层的上表面凹陷以暴露所述鳍片的一部分，执行 氧化过程，以便氧化鳍片的至少一部分并在鳍的暴露部分中形成具有大于第一锗浓度的第二锗浓度的区域，从在第一锗浓度期间形成的翅片上除去氧化物材料 氧化工艺并形成位于至少具有第二锗浓度的区域周围的栅极结构。

公开(公告)号：US20190273148A1

公开(公告)日：2019-09-05

申请号：US16415519

申请日：2019-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10325811B2

公开(公告)日：2019-06-18

申请号：US15794600

申请日：2017-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco ,  Wei Zhao ,  Haiting Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.

公开(公告)号：US10002793B1

公开(公告)日：2018-06-19

申请号：US15464591

申请日：2017-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  David P. Brunco ,  Jinping Liu ,  Baofu Zhu ,  Shesh Mani Pandey

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/225

CPC classification number: H01L21/2254 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823892

Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.

公开(公告)号：US10811422B2

公开(公告)日：2020-10-20

申请号：US16196060

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Wei Hong ,  Hui Zang ,  David P. Brunco

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/08

Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.