公开(公告)号：US06483715B1

公开(公告)日：2002-11-19

申请号：US09989419

申请日：2001-11-21

Applicant: Michael Chen

Inventor： Michael Chen

IPC: H05K116

CPC classification number: H05K1/0228 ,  H01R13/6466 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A circuit board coupled with jacks and conformed to Category 6 standard has conductors to connect IDC contacts and jack pins to reduce cross-talk and improve return-loss. The improvements are targeted on the pair 1 and 3 conductors of circuit conductors, and include forming capacitors by main conductors connecting to the IDC and jack on two sides of the circuit board, extending pair 1 and 3 conductor ends in the vicinity of IDC junctures to form a TR (or TT,RR) conductor layout, and extending pair 1 and 3 conductor ends in the vicinity of jack junctures to form a TT or RR conductor layout (or TT for IDC end, or RR for jack end) to generate induction effect, thereby to form the circuit board coupled with jacks that has circuit conductors laid on two sides thereof and conforms to Category 6 communication standard.

Abstract translation: 与插座配合并符合6类标准的电路板具有用于连接IDC触点和插座引脚的导体，以减少串扰并提高回波损耗。 这些改进针对电路导体的1对和3导体，并且包括通过连接到电路板两侧的IDC和插座的主导体形成电容器，在IDC接合点附近延伸对1和3导体端部到 形成TR（或TT，RR）导体布局，并在插座接点附近扩展对1和3导体端，以形成TT或RR导体布局（或IDC端的TT或插孔端的RR）以产生感应 从而形成与具有布置在其两侧上的电路导体并且符合类别6通信标准的插座耦合的电路板。

公开(公告)号：US6097260A

公开(公告)日：2000-08-01

申请号：US9861

申请日：1998-01-22

Applicant: Walter M. Whybrew ,  Jeffery C. May ,  Douglas E. Heckaman

Inventor： Walter M. Whybrew ,  Jeffery C. May ,  Douglas E. Heckaman

IPC: H01P3/08 ,  H05K1/02 ,  H05K3/42 ,  H01P5/12

CPC classification number: H01P3/085 ,  H01P3/088 ,  H05K1/0219 ,  H05K2201/09245 ,  H05K2201/09254 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K3/429

Abstract: A distributed ground pad-based isolation arrangement for a multilayer stripline architecture is configured to effectively inhibit the mutual coupling of signals between overlapping regions of adjacent stripline networks of dielectrically separated transmission networks, without substantially increasing either the mass of the laminate structure or the lossiness of the stripline. At regions of mutual overlap, the stripline layers are spatially oriented at right angles to one another, and a limited area ground pad is interleaved between the stripline layers. To maintain the desired characteristic line impedance of a stripline layer as it passes over a ground pad, the width of the stripline layer is reduced in the overlap region. Each ground pad is connected to an external ground reference by plated vias, that extend through the dielectric layers and intersect outer grounded shielding layers of the laminate.

Abstract translation: 用于多层带状线结构的分布式接地垫隔离装置被配置为有效地抑制相互间隔分离的传输网络的相邻带状线网络的重叠区域之间的信号的相互耦合，而基本上不增加层压结构的质量或者层压结构的损耗 带状线。 在相互重叠的区域中，带状线层在空间上彼此成直角定向，并且有限区域接地焊盘在带状线层之间交错。 为了在带状线层通过接地焊盘时保持所需的特征线阻抗，带状线层的宽度在重叠区域中减小。 每个接地焊盘通过电镀通孔连接到外部接地参考，其通过电介质层延伸并与叠层的外部接地屏蔽层相交。

公开(公告)号：US06081022A

公开(公告)日：2000-06-27

申请号：US317787

申请日：1999-05-24

Applicant: Sundari S. Mitra ,  Aleksandar Pance

Inventor： Sundari S. Mitra ,  Aleksandar Pance

IPC: H01L23/522 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H01L23/58

CPC classification number: H01L23/5383 ,  H01L23/5225 ,  H05K1/0219 ,  H01L2924/0002 ,  H05K1/0289 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09618 ,  H05K2201/09809

Abstract: An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505 . . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . . ) are electrically connected to the ground lines (201, 203) with vias (603A, 603B, 605A, 605B . . . ). In the same metal layer as the conductive regions, conductive signal lines (509, 511) are routed between the regions (501, 503, 505, 507 . . . ) to cross below the clock line. The conductive regions (501, 503, 505, 507 . . . ) form a shield between the clock line (101) and any signal lines (105) routed in the next metal layer adjacent to the metal layer containing the conductive regions.

Abstract translation: 互连结构包括在第一层中的时钟线和基本上平行于时钟线延伸的接地线，以及位于与第一层平行的第二层中的多个导电区域。 接地线耦合到地电位源。 导电区域与时钟线对准，并且设置在跨越时钟线的第二层中路由的信号线周围。 导电区域电连接到接地线，从而形成用于时钟线的屏蔽，其有助于防止在时钟线上传播的时钟信号与其它信号线电磁耦合。 在一个实施例中，时钟分配网络包括在时钟线层下方的金属层中的导电区域（501,503,505 ...）和与时钟线相同的金属层中的两个并行接地线（201,203） 101）。 导电区域（501,503,505 ...）通过通孔（603A，603B，605A，605B ...）电连接到接地线路（201,203）。 在与导电区域相同的金属层中，导电信号线路（509,511）在区域（501,503,505,507 ...之间）之间布线以在时钟线下方交叉。 导电区域（501,503,505,507 ...）在时钟线（101）和与包含导电区域的金属层相邻的下一个金属层中布线的任何信号线（105）之间形成屏蔽。

公开(公告)号：US5994765A

公开(公告)日：1999-11-30

申请号：US673490

申请日：1996-07-01

Applicant: Sundari S. Mitra ,  Aleksandar Pance

Inventor： Sundari S. Mitra ,  Aleksandar Pance

IPC: H01L23/522 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H01L23/552 ,  H01L23/48 ,  H01L23/58 ,  H01L27/10

CPC classification number: H01L23/5383 ,  H01L23/5225 ,  H05K1/0219 ,  H01L2924/0002 ,  H05K1/0289 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09618 ,  H05K2201/09809

Abstract: An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505. . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .) are electrically connected to the ground lines (201, 203) with vias (603A, 603B, 605A, 605B . . . ). In the same metal layer as the conductive regions, conductive signal lines (509, 511) are routed between the regions (501, 503, 505, 507. . . ) to cross below the clock line. The conductive regions (501, 503, 505, 507. . . ) form a shield between the clock line (101) and any signal lines (105) routed in the next metal layer adjacent to the metal layer containing the conductive regions.

Abstract translation: 互连结构包括在第一层中的时钟线和基本上平行于时钟线延伸的接地线，以及位于与第一层平行的第二层中的多个导电区域。 接地线耦合到地电位源。 导电区域与时钟线对准，并且设置在跨越时钟线的第二层中路由的信号线周围。 导电区域电连接到接地线，从而形成用于时钟线的屏蔽，其有助于防止在时钟线上传播的时钟信号与其它信号线电磁耦合。 在一个实施例中，时钟分配网络包括在时钟线层下方的金属层中的导电区域（501,503,505 ...）和与时钟线相同的金属层中的两个并行接地线（201,203） 101）。 导电区域（501,503,505 ...）通过通孔（603A，603B，605A，605B ...）电连接到接地线路（201,203）。 在与导电区域相同的金属层中，导电信号线路（509,511）在区域（501,503,505,507 ...）之间布线以在时钟线下方交叉。 导电区域（501,503,505,507 ...）在时钟线（101）和与包含导电区域的金属层相邻的下一个金属层中布线的任何信号线（105）之间形成屏蔽。

公开(公告)号：US5915989A

公开(公告)日：1999-06-29

申请号：US922942

申请日：1997-09-03

Applicant: Luc W. Adriaenssens ,  Amid I. Hashim ,  William J. Ivan ,  Troy P. Million ,  Bryan S. Moffitt

Inventor： Luc W. Adriaenssens ,  Amid I. Hashim ,  William J. Ivan ,  Troy P. Million ,  Bryan S. Moffitt

IPC: H01R4/24 ,  H01R24/00 ,  H05K1/02 ,  H05K1/16

CPC classification number: H01R13/6464 ,  H05K1/0228 ,  H01R13/6474 ,  H01R4/2429 ,  H05K1/0231 ,  H05K1/162 ,  H05K2201/09245 ,  H05K2201/10189

Abstract: Connectors, such as 110-type patch plugs, are designed to reduce near-end crosstalk that is generated when the connector is mated to a corresponding receptacle, such as a 110-type connecting block. Connectors of the present invention employ a two-stage crosstalk compensation scheme in which a first stage induces a compensating crosstalk signal, having opposite polarity as the original crosstalk signal, while the second stage induces a counter-balancing crosstalk signal, having same polarity as the original crosstalk signal. The two-stage, counter-balanced crosstalk compensation scheme of the present invention takes into account both the magnitude of the original crosstalk signal as well as the phase differences between the original crosstalk signal and the compensating and counter-balancing crosstalk signals that result from the different locations along the signal path at which the crosstalk signals are induced. The contacts of the connector are designed such that the magnitudes and locations of the compensating and counter-balancing crosstalk signals provide effective crosstalk compensation over a particular range of frequencies, e.g., 1 MHz to 200 MHz.

Abstract translation: 连接器，例如110型接插件，被设计用于减少当连接器与相应插座（例如110型连接块）配合时产生的近端串扰。 本发明的连接器采用两级串扰补偿方案，其中第一级引起具有与原始串扰信号相反极性的补偿串扰信号，而第二级感应出具有与原始串扰信号相同极性的反平衡串扰信号 原始串扰信号。 本发明的两级反平衡串扰补偿方案考虑了原始串扰信号的大小以及原始串扰信号与由均衡信号产生的补偿和反平衡串扰信号之间的相位差 沿着引起串扰信号的信号路径的不同位置。 连接器的触点被设计成使得补偿和反平衡串扰信号的幅度和位置在特定频率范围（例如1MHz至200MHz）上提供有效的串扰补偿。

公开(公告)号：US5414393A

公开(公告)日：1995-05-09

申请号：US2871

申请日：1993-01-15

Applicant: William J. Rose ,  Robert Aekins

Inventor： William J. Rose ,  Robert Aekins

IPC: H01R13/6469 ,  H01R13/6473 ,  H05K1/02 ,  H05K1/11 ,  H03H7/00 ,  H04M1/74

CPC classification number: H01R13/6469 ,  H01R13/6473 ,  H05K1/0228 ,  H05K1/117 ,  H05K2201/09245 ,  H05K2201/097 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A connector for communications systems has four input terminals and four output terminals, each arranged in an ordered array. A circuit electrically couples each input terminal to the respective output terminal and cancels crosstalk induced across the adjacent connector terminals. The circuit includes four conductive paths between the respective pairs of terminals. Each conductive path includes a plurality of conductive strips arranged in a zig-zag pattern with alternating strips mounted on opposite sides of the substrate and connected end-to-end by conductive devices passing through the substrate. The first and third paths are in relatively close proximity with conductive strips of the first path crossing conductive strips of the third path on opposite sides of the substrate to simulate a twisted wiring pair. The second and fourth paths are in relatively close proximity with conductive strips of the second path crossing conductive strips of the fourth path on opposite sides of the substrate to simulate a twist wiring pair.

Abstract translation: 用于通信系统的连接器具有四个输入端子和四个输出端子，每个输出端子以有序阵列布置。 电路将每个输入端子电耦合到相应的输出端子，并且消除在相邻的连接器端子之间引起的串扰。 该电路包括在各对端子之间的四个导电路径。 每个导电路径包括以锯齿形图案布置的多个导电条，其中交替的带安装在基板的相对侧上，并且通过穿过基板的导电装置端对端地连接。 第一和第三路径相对靠近第一路径的导电条，其与衬底的相对侧上的第三路径的导电条交叉，以模拟双绞线对。 第二和第四路径相对靠近第二路径的导电条，其与衬底的相对侧上的第四路径的导电条交叉，以模拟扭转线对。

公开(公告)号：US5299956A

公开(公告)日：1994-04-05

申请号：US855893

申请日：1992-03-23

Applicant: Kenneth W. Brownell ,  Sterling A. Vaden

Inventor： Kenneth W. Brownell ,  Sterling A. Vaden

IPC: H04B3/32 ,  H05K1/02 ,  H01R13/00

CPC classification number: H05K1/0228 ,  H01R13/6469 ,  H04B3/32 ,  H01R24/64 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: There is provided an apparatus for reducing pair to pair cross talk which arises in electrical connectors due to closely spaced elongated parallel contacts. The cross talk which occurs within the connector is reduced by modifying certain circuit paths either inside or outside of the connector so that each conductor of a first pair which is parallel to and cross talking with an adjacent conductor of a second pair in the connector is relocated adjacent and parallel to the other conductor of the second pair over a predetermined distance. It is preferred that the relocation of the circuit paths occur on a circuit board which is attached to the connector.

Abstract translation: 提供了一种用于减少由于紧密间隔的细长平行触点而在电连接器中产生的配对串扰的装置。 通过修改连接器内部或外部的某些电路路径来减少连接器内的串扰，使得与连接器中的第二对的相邻导体平行并与之交叉的第一对导体的每个导体被重新定位 相邻并平行于第二对的另一导体预定距离。 优选地，电路路径的重定位发生在连接到连接器的电路板上。

公开(公告)号：US5269708A

公开(公告)日：1993-12-14

申请号：US019008

申请日：1993-03-03

Applicant: David M. DeYoung ,  William A. Kinghorn

Inventor： David M. DeYoung ,  William A. Kinghorn

IPC: H01R9/24 ,  H04Q1/14 ,  H05K1/02 ,  H01R13/00

CPC classification number: H05K1/0228 ,  H01R13/6469 ,  H04Q1/13 ,  H01R12/515 ,  H01R24/64 ,  H04Q2201/12 ,  H05K2201/09245 ,  H05K2201/09263

Abstract: A patch panel includes a printed circuit board, an RJ-45 jack and a connector block. The circuit paths from the RJ-45 jack to the connector block are selected to cross in a predetermined crossing pattern with the circuit paths having a predetermined length selected for the patch panel to carry high speed transmissions.

Abstract translation: 接线板包括印刷电路板，RJ-45插孔和连接器块。 选择从RJ-45插座到连接器块的电路路径以预定的交叉图案交叉，电路路径具有为接线板选择的预定长度以承载高速传输。

公开(公告)号：US4568987A

公开(公告)日：1986-02-04

申请号：US563433

申请日：1983-12-20

Applicant: Kazuaki Ishiwata

Inventor： Kazuaki Ishiwata

IPC: G11B5/02 ,  G11B5/027 ,  G11B20/24 ,  H03F1/26 ,  H03F3/183 ,  H05K1/02 ,  H05K1/16 ,  G11B5/00

CPC classification number: G11B20/24 ,  G11B5/02 ,  H03F1/26 ,  H03F3/183 ,  H05K1/0228 ,  H05K1/165 ,  H05K2201/0792 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10015 ,  H05K2201/10166

Abstract: Disclosed is a circuit arrangement having an amplifier with first and second input terminals which are adapted to be coupled to a playback head, wherein the first input terminal of the amplifier is coupled through a first circuit section of a conductive pattern to a first terminal of the playback head and the second input terminal of the amplifier is coupled through a second circuit section of the conductive pattern to a second terminal of the playback head. The first and second circuit sections (3, 4) are arranged to insulatively cross each other at an intersection (6) to form a figure eight pattern having two loop sections of substantially equal areas to equalize the amounts of currents which are oppositely respectively induced in the first and second loop sections by an externally generated magnetic flux.

Abstract translation: 公开了具有放大器的电路装置，该放大器具有适于耦合到重放头的第一和第二输入端，其中放大器的第一输入端通过导电图案的第一电路部分耦合到 放大器的第一和第二输入端通过导电图案的第二电路部分耦合到重放头的第二端。 第一和第二电路部分（3,4）被布置成在交叉点（6）处彼此绝对交叉以形成具有基本上相等面积的两个环路部分的图形八模式，以均衡相应地分别诱发的电流量 第一和第二环路部分由外部产生的磁通量。