公开(公告)号：US20200295000A1

公开(公告)日：2020-09-17

申请号：US16891992

申请日：2020-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

公开(公告)号：US10763362B2

公开(公告)日：2020-09-01

申请号：US16050703

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/283 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A FinFET device structure and method for forming the same are provided. The Fin PET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

公开(公告)号：US20200243520A1

公开(公告)日：2020-07-30

申请号：US16845102

申请日：2020-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US10727132B2

公开(公告)日：2020-07-28

申请号：US15646078

申请日：2017-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/84

Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

公开(公告)号：US10468348B2

公开(公告)日：2019-11-05

申请号：US15891394

申请日：2018-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/768

Abstract: A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric layer is etched to form a recess. A dummy adhesion layer is deposited on sidewalls of the recess. A conductive layer is formed in the recess. The dummy adhesion layer is removed to expose a portion of the conductive layer.

公开(公告)号：US20190259849A1

公开(公告)日：2019-08-22

申请号：US16404017

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

Abstract: A method includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench and forming a hard mask (HM) layer in a space in the gate trench and surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench and depositing a metal layer in the gate trench. The metal layer is in physical contact with a sidewall surface of the gate WF layer that is deposited before the HM layer is formed.

公开(公告)号：US10366926B1

公开(公告)日：2019-07-30

申请号：US16390246

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321

CPC classification number: H01L21/823431 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

公开(公告)号：US10283605B2

公开(公告)日：2019-05-07

申请号：US15287509

申请日：2016-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L21/76 ,  H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench, and forming a hard mask (HM) layer in a space surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench. After the removing of the HM layer, the method further includes depositing a metal layer in the gate trench.

公开(公告)号：US10263090B2

公开(公告)日：2019-04-16

申请号：US15726113

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han Lin ,  Shih-Chang Tsai ,  Wen-Shuo Hsieh ,  Te-Yung Liu

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/786 ,  H01L27/04 ,  H01L21/02 ,  H01L51/52 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device is provided including an opening in a gate electrode layer to form two spaced apart gate electrode layers. An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers. A first insulating layer is formed in the opening between the two spaced apart gate electrode layers.

公开(公告)号：US10205004B2

公开(公告)日：2019-02-12

申请号：US15900748

申请日：2018-02-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor fin on the semiconductor substrate and a fin isolation structure on the semiconductor substrate. The fin isolation structure has an air gap dividing the semiconductor fin into two portions of the semiconductor fin, in which the air gap extends into the semiconductor substrate for a distance. The fin isolation structure includes a dielectric cap layer capping a top of the air gap, in which the dielectric cap layer is spaced apart from a bottom of the air gap.