公开(公告)号：US12156473B2

公开(公告)日：2024-11-26

申请号：US16631681

申请日：2017-09-20

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Nicholas James Harold McKubre ,  Han Wui Then

IPC: H01L41/09 ,  H01F27/24 ,  H01F27/30 ,  H01L49/02 ,  H10N30/20

Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.

公开(公告)号：US12154855B2

公开(公告)日：2024-11-26

申请号：US16579088

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Reken Patel ,  Richard E. Schenker ,  Charles H. Wallace

IPC: H01L23/528 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02

Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.

公开(公告)号：US12154638B2

公开(公告)日：2024-11-26

申请号：US17353493

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Renzhi Liu ,  Deepak Dasalukunte

IPC: G11C27/02 ,  G06N3/063

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

公开(公告)号：US12154309B2

公开(公告)日：2024-11-26

申请号：US18462305

申请日：2023-09-06

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Yun Ren ,  Hao Zhao ,  Tao Kong ,  Yurong Chen

IPC: G06V10/00 ,  G06F18/243 ,  G06N3/04 ,  G06N3/08 ,  G06V10/44 ,  G06V10/82 ,  G06V20/10 ,  G06V20/70 ,  G06V30/19 ,  G06V30/24

Abstract: An example apparatus for mining multi-scale hard examples includes a convolutional neural network to receive a mini-batch of sample candidates and generate basic feature maps. The apparatus also includes a feature extractor and combiner to generate concatenated feature maps based on the basic feature maps and extract the concatenated feature maps for each of a plurality of received candidate boxes. The apparatus further includes a sample scorer and miner to score the candidate samples with multi-task loss scores and select candidate samples with multi-task loss scores exceeding a threshold score.

公开(公告)号：US12153920B2

公开(公告)日：2024-11-26

申请号：US16714680

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Mohamed Elmalaki ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/30

Abstract: Systems, methods, and apparatuses relating to instructions to multiply values of one are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number; and an execution circuit to execute the decoded single instruction to: cause a first comparison of the first number to a one value in the number format of the first number, cause a second comparison of the second number to a one value in the number format of the second number, provide as a resultant of the single instruction the first number when the second comparison indicates the second number equals the one value in the number format of the second number, provide as the resultant of the single instruction the second number when the first comparison indicates the first number equals the one value in the number format of the first number, and provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the one value in the number format of the first number and the second comparison indicates the second number does not equal the one value in the number format of the second number.

公开(公告)号：US12153823B2

公开(公告)日：2024-11-26

申请号：US17068369

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Davide Fugazza ,  Dany-Sebastien Ly-Gagnon ,  DerChang Kau

IPC: G11C11/56 ,  G06F3/06 ,  G11C13/00 ,  H10N70/00

Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.

公开(公告)号：US20240389294A1

公开(公告)日：2024-11-21

申请号：US18319717

申请日：2023-05-18

Applicant: Intel Corporation

Inventor： Denzil Frost

IPC: H10B10/00

Abstract: Described herein are SRAM cells in which some transistors are implemented as thin film transistors (TFTs) while other transistors are implemented as non-TFTs (e.g., as FinFETs or nanoribbon-based transistors), where the TFTs are folded over non-TFTs to realize high-density 3D SRAM. For a given SRAM cell, either N-type transistors may be implemented as TFTs and stacked above P-type transistors that are implemented as non-TFTs, or P-type transistors may be implemented as TFTs and may be stacked above N-type transistors that are implemented as non-TFTs.

公开(公告)号：US20240386272A1

公开(公告)日：2024-11-21

申请号：US18785849

申请日：2024-07-26

Applicant: Intel Corporation

Inventor： Yamini Nimmagadda ,  Susanne M. Balle ,  Olugbemisola Oniyinde

IPC: G06N3/08 ,  G06F9/50 ,  G06N3/063

Abstract: An Infrastructure Processing Unit (IPU), including: a model optimization processor configured to optimize an artificial intelligence (AI) model for an accelerator managed by the IPU, and deploy the optimized AI model to the accelerator for execution of an inference; and a local memory configured to store data related to the AI model optimization.

公开(公告)号：US20240385754A1

公开(公告)日：2024-11-21

申请号：US18570674

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Daocheng BU ,  Dujian WU ,  Yufu LI ,  Vincent ZIMMER

IPC: G06F3/06

Abstract: Various examples relate to a control apparatus, a control device, a method, and a computer program for managing repair of a memory circuitry, and to a corresponding computing device. The control apparatus comprises processing circuitry configured to determine a score of a memory failure probability of at least one memory cell of the memory circuitry and trigger a repair procedure of the at least one memory cell of the memory circuitry when the score reaches a threshold.

公开(公告)号：US20240382045A1

公开(公告)日：2024-11-21

申请号：US18415525

申请日：2024-01-17

Applicant: Haws Corporation ,  Intel Corporation

Inventor： Danté DeSimone ,  Stephen Stanley ,  Ryan Fick

IPC: A47K3/40

Abstract: A universal drain pan that comprises a substantially flat base portion with four upright portions is provided. Along a plurality of the upright portions are installed threaded side drains. These side drains, which may be used or plugged as required in the field, are mounted just above the bottom face of the drain pan and incorporate a downward-facing slit to allow a pump to draw a maximum volume of water out of the pan.