公开(公告)号：US20180337806A1

公开(公告)日：2018-11-22

申请号：US15978506

申请日：2018-05-14

Applicant: Rambus Inc.

Inventor： Ramin Farjad-Rad

IPC: H04L25/03 ,  H04L25/08

CPC classification number: H04L25/03159 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/085 ,  H04L2025/03681

Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

公开(公告)号：US10135646B2

公开(公告)日：2018-11-20

申请号：US15827777

申请日：2017-11-30

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US10135642B2

公开(公告)日：2018-11-20

申请号：US15438571

申请日：2017-02-21

Applicant: Rambus Inc.

Inventor： Marko Aleksić ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

IPC: H03H7/30 ,  H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

公开(公告)号：US10120600B2

公开(公告)日：2018-11-06

申请号：US15728936

申请日：2017-10-10

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Collins Williams ,  Dan Kunkel ,  William Wolf

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G06F12/0802

Abstract: The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

公开(公告)号：US10114775B2

公开(公告)日：2018-10-30

申请号：US15277949

申请日：2016-09-27

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/362 ,  H01L23/60 ,  H01L25/065 ,  G11C11/408 ,  G11C11/409 ,  H01L23/50 ,  H01L23/00 ,  G06F13/40 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L27/02 ,  H01L23/48

Abstract: This application is directed to a stacked semiconductor device assembly including first and second integrated circuit (IC) devices. Each of the first and second IC devices further includes a master interface, a channel master circuit configured to receive read/write data using the master interface, a slave interface, a channel slave circuit configured to receive read/write data using the slave interface, a memory core coupled to the channel salve circuit, and a modal pad. The first and second IC devices are configured such that in response to at least a modal selection signal received at one of the modal pads of the first and second IC devices, one of the first and second IC devices is configured to receive read/write data using its respective charnel master circuit, and the other of the first and second IC devices is configured to receive read/write data using its respective channel slave circuit.

公开(公告)号：US10102885B2

公开(公告)日：2018-10-16

申请号：US15841049

申请日：2017-12-13

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: H04B15/00 ,  G11C5/14 ,  G06F11/07

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US10102140B2

公开(公告)日：2018-10-16

申请号：US15393232

申请日：2016-12-28

Applicant: RAMBUS INC.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/0811

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US20180287776A1

公开(公告)日：2018-10-04

申请号：US15907200

申请日：2018-02-27

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe

IPC: H04L7/033 ,  H04L7/00

Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

公开(公告)号：US10091036B1

公开(公告)日：2018-10-02

申请号：US15624556

申请日：2017-06-15

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Maruf H. Mohammad

IPC: H03H7/30 ,  H04L25/49 ,  H04L25/03

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

公开(公告)号：US20180278440A1

公开(公告)日：2018-09-27

申请号：US15761938

申请日：2016-08-03

Applicant: RAMBUS INC.

Inventor： Yikui Jen Dong

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  G11C7/1057 ,  G11C7/1069 ,  G11C2207/107 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/03 ,  H04L25/03012 ,  H04L25/03878 ,  H04L25/03885

Abstract: A transmitting device includes an output node, at least one driver circuit and transition equalization circuitry. The driver circuit drives an output data signal including a data transition onto the output node. The output of the transition equalization circuitry is coupled to the output node. The transition equalization circuitry begins to drive the output node at the data transition and ends driving of the output node a pre-determined delay after beginning to drive the output node. The transition equalization circuitry drives the output node by injecting current onto the output node if the data transition is a positive transition, and sinking current from the output node if the data transition is a negative transition.